Henri Richard Confirms K8L CPU Core, Some Details
March 14, 2006 2:40 PM
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In a recent interview, AMD's next generation CPU architecture gets a name and a socket
Digitimes has a
to its interview with AMD's Henri Richard. We covered the first
interview here yesterday
. Digitimes tried to squeeze a few more details out of Richard about the upcoming K8L platform architecture. In the first interview, Richard would not comment on K8L.
That's not to say we're going to present K8L at Computex – don't get me wrong – but I think that that would be a good time to start to disclose more about the future because one of the strong attributes of our roadmap, both in 2006 and 2007, is socket compatibility. The nice thing we're going to do is to deliver to customers. Whatever improvements K8L will provide, they will be applicable to some of the sockets we will be introducing. Therefore, there's a certain logic, to my mind, in disclosing more at that time.
In the first interview, Richard referred to the new architecture as "8KL" instead, but Digitimes reporters did not get back to us about this idiosyncrasy. The three sockets AMD has on the roadmap are the
1207 pin LGA Socket F for servers
for the desktop and
for mobile devices. All three are expected to have working samples on June 6th, 2006 according to AMD's most recent roadmap.
In response to the approach AMD will take with K8L, Richard previously claimed that
future AMD micro-architectures are strictly evolutionary and not revolutionary
. In yesterday's interview, he also claimed that AMD will arrive at better performance by improving clock speeds and increasing cache sizes, but that future core technologies will have increased integer and floating-point performance. Seeing as K8L is the only technology on the AMD roadmap for the next year or so after AM2, we can only speculate as to what Richard means by that statement.
Chris Hall from Digitimes has confirmed with us that the "8KL" reference was a misquote and that Richard was really referring to K8L.
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RE: Clock and Cache
3/15/2006 2:32:16 PM
Simple AMD and Intel both talk about how great their future products and processes are. In AMD's case I heave heard something about 40% better transistor performance compared to a generic 65nm process and that Z-RAM tech about 5 times better cache desnity, without a shred of evidence to back this up jsut their word.
Conroe is a different story however, that as we know is a good product without a doubt.
As always just because they have access to this doesn't mean it will be implemented that quickly, if and when AMD improves their cache densities in an actual product and not just hype some tech that they had acquired is when I will believe they can increase their cache densities.
For the moment their cache density will remain inferior at least until they move to the 65nm process. Though cache desnity has already been improved on the Windsor core Athlon64x2.
"And boy have we patented it!" -- Steve Jobs, Macworld 2007
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