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In a recent interview, AMD's next generation CPU architecture gets a name and a socket

Digitimes has a follow up to its interview with AMD's Henri Richard.  We covered the first interview here yesterday. Digitimes tried to squeeze a few more details out of Richard about the upcoming K8L platform architecture.  In the first interview, Richard would not comment on K8L. 

That's not to say we're going to present K8L at Computex – don't get me wrong – but I think that that would be a good time to start to disclose more about the future because one of the strong attributes of our roadmap, both in 2006 and 2007, is socket compatibility. The nice thing we're going to do is to deliver to customers. Whatever improvements K8L will provide, they will be applicable to some of the sockets we will be introducing. Therefore, there's a certain logic, to my mind, in disclosing more at that time.

In the first interview, Richard referred to the new architecture as "8KL" instead, but Digitimes reporters did not get back to us about this idiosyncrasy.  The three sockets AMD has on the roadmap are the 1207 pin LGA Socket F for servers, Socket AM2 for the desktop and Socket S1 for mobile devices.  All three are expected to have working samples on June 6th, 2006 according to AMD's most recent roadmap. 

In response to the approach AMD will take with K8L, Richard previously claimed that future AMD micro-architectures are strictly evolutionary and not revolutionary.  In yesterday's interview, he also claimed that AMD will arrive at better performance by improving clock speeds and increasing cache sizes, but that future core technologies will have increased integer and floating-point performance.  Seeing as K8L is the only technology on the AMD roadmap for the next year or so after AM2, we can only speculate as to what Richard means by that statement. 

Update 03/15/2006: Chris Hall from Digitimes has confirmed with us that the "8KL" reference was a misquote and that Richard was really referring to K8L.

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RE: Die size
By Viditor on 3/15/2006 8:29:37 AM , Rating: 2
the die size for Conroe is really quite a lot smaller than the die size for the Athlon 64 at the moment, isn't it?

I have yet to see a die size number from Intel on the various Conroe chips, but:
X2 @ 1MB cache 90nm = 147 mm2
X2 @ 2MB cache 90nm = 199 mm2
Pressler @ 4MB cache 65nm = 140 mm2
Pentium D @ 2MB cache 90nm = 213mm2

As a WAG, I'd bet that Conroe will be around 140 mm2 for the 4MB as well, and ~105 mm2 for the 2MB variety.

Intel currently gets better density than AMD does on their L2, but AMD signed a license in Dec for a new type of cache memory called Z-Ram, which increases density up to five times their current density. It only works on SOI chips, but one of the cool things about it is that it requires just a fraction of the power that current types of cache use.

RE: Die size
By coldpower27 on 3/15/2006 2:25:45 PM , Rating: 2
No not quite on the Die size on the Pentium D's.

Smithfield = Monolithic 206mm2 die. 2x1MB
Presler = Dual Die 2x81mm2 dice. 2x2MB

What should be noted is that:
Manchester = 147mm2 2x512kb S939
Toledo = 199mm2 2x1MB S939
Windsor = 220mm2 2x1MB SAM2

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