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In a recent interview, AMD's next generation CPU architecture gets a name and a socket

Digitimes has a follow up to its interview with AMD's Henri Richard.  We covered the first interview here yesterday. Digitimes tried to squeeze a few more details out of Richard about the upcoming K8L platform architecture.  In the first interview, Richard would not comment on K8L. 

That's not to say we're going to present K8L at Computex – don't get me wrong – but I think that that would be a good time to start to disclose more about the future because one of the strong attributes of our roadmap, both in 2006 and 2007, is socket compatibility. The nice thing we're going to do is to deliver to customers. Whatever improvements K8L will provide, they will be applicable to some of the sockets we will be introducing. Therefore, there's a certain logic, to my mind, in disclosing more at that time.

In the first interview, Richard referred to the new architecture as "8KL" instead, but Digitimes reporters did not get back to us about this idiosyncrasy.  The three sockets AMD has on the roadmap are the 1207 pin LGA Socket F for servers, Socket AM2 for the desktop and Socket S1 for mobile devices.  All three are expected to have working samples on June 6th, 2006 according to AMD's most recent roadmap. 

In response to the approach AMD will take with K8L, Richard previously claimed that future AMD micro-architectures are strictly evolutionary and not revolutionary.  In yesterday's interview, he also claimed that AMD will arrive at better performance by improving clock speeds and increasing cache sizes, but that future core technologies will have increased integer and floating-point performance.  Seeing as K8L is the only technology on the AMD roadmap for the next year or so after AM2, we can only speculate as to what Richard means by that statement. 

Update 03/15/2006: Chris Hall from Digitimes has confirmed with us that the "8KL" reference was a misquote and that Richard was really referring to K8L.

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I believe these were the benchmark parameters
By DallasTexas on 3/14/2006 6:11:42 PM , Rating: -1
I'm pretty sure that the benchmark where AMD's chip got creamed included the following parameters:

- Overclock the FX60 just before it bursts into flames (like the AMD K5 did... or does)
- Use a Celeron version of Conroe clocked for the entry level
- Turn off the Conroe's cache

I might be off with the above. Please check

By smitty3268 on 3/14/2006 6:30:44 PM , Rating: 2
- Overclock the FX60 just before it bursts into flames (like the AMD K5 did... or does)

Well, it was an average OC on a poorly OCing chip. AMD is probably going to have to come out with a new revision before they can bump up the clock speed too much, but its not like that was the highest OC ever done.

- Use a Celeron version of Conroe clocked for the entry level

No, this was not the cheapo version of Conroe. It would be about like a 3.6GHz Prescott right now. Fast, but there are a few steps above, especially the EE chips.

- Turn off the Conroe's cache

What? You can't turn off cache - or at least not easily outside of the factory. This chip had the full 4MB L2 cache, while cheaper versions (not benchmarked yet) will only have 2MB.

By Xenoterranos on 3/14/2006 7:05:48 PM , Rating: 2
LOL, I would buy a case of chips that could attain that performance without cache!

By Missing Ghost on 3/14/2006 7:15:29 PM , Rating: 2
I have settings to disable the caches in my computer's bios settings.

By smitty3268 on 3/14/2006 7:24:47 PM , Rating: 2
Well, it certainly isn't impossible if the hardware support is there. The Pentium M will turn off portions of its cache on-the-fly to save power. But I fail to see why anyone would think that Intel would completely disable their cache on a chip they are benchmarking. And the original post made it sound like they went into Windows Control Panel and selected "Turn off cache" or something to that affect - maybe I just read it wrong.

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