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In a recent interview, AMD's next generation CPU architecture gets a name and a socket

Digitimes has a follow up to its interview with AMD's Henri Richard.  We covered the first interview here yesterday. Digitimes tried to squeeze a few more details out of Richard about the upcoming K8L platform architecture.  In the first interview, Richard would not comment on K8L. 

That's not to say we're going to present K8L at Computex – don't get me wrong – but I think that that would be a good time to start to disclose more about the future because one of the strong attributes of our roadmap, both in 2006 and 2007, is socket compatibility. The nice thing we're going to do is to deliver to customers. Whatever improvements K8L will provide, they will be applicable to some of the sockets we will be introducing. Therefore, there's a certain logic, to my mind, in disclosing more at that time.

In the first interview, Richard referred to the new architecture as "8KL" instead, but Digitimes reporters did not get back to us about this idiosyncrasy.  The three sockets AMD has on the roadmap are the 1207 pin LGA Socket F for servers, Socket AM2 for the desktop and Socket S1 for mobile devices.  All three are expected to have working samples on June 6th, 2006 according to AMD's most recent roadmap. 

In response to the approach AMD will take with K8L, Richard previously claimed that future AMD micro-architectures are strictly evolutionary and not revolutionary.  In yesterday's interview, he also claimed that AMD will arrive at better performance by improving clock speeds and increasing cache sizes, but that future core technologies will have increased integer and floating-point performance.  Seeing as K8L is the only technology on the AMD roadmap for the next year or so after AM2, we can only speculate as to what Richard means by that statement. 

Update 03/15/2006: Chris Hall from Digitimes has confirmed with us that the "8KL" reference was a misquote and that Richard was really referring to K8L.



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RE: Clock and Cache
By JackPack on 3/14/2006 5:32:31 PM , Rating: 3
Just because Conroe _may_ be heavily affected by cache does not mean the same will be true for K8. Conroe also uses a shared L2, while K8 does not.

K8 already has a low latency path to the main memory. Chances are, adding cache will not help much with performance.


RE: Clock and Cache
By blckgrffn on 3/14/2006 5:49:43 PM , Rating: 3
Not entirely true. L2 cache is much faster than main memory and if applications can use 4 megs of local cache, then so much the better.

Don't forget you have to add the latency of the level 1 cache, the level 2 cache, and the latency of main memory to get the total latency of the ram (level 3 in the hiearchy in this case). Have a larger L2 cache will keep more memory requests from having to transverse this far.

Also, the conroe in question did indeed have 4 megs of L2 cache. The latency is unknown at this time, I believe. AMD could also enhance the speed of their L2 cache by increasing the number of sets and therefore decreasing the set size. My guess is if they do go with a larger cache, however, they will keep it the same latency as the current one. Making it faster is expensive, just check out the prescott 1 meg to 2 meg cache increase to see this and why the speed is also important.


RE: Clock and Cache
By Xenoterranos on 3/14/2006 7:14:57 PM , Rating: 2
You forget that the memory crossbar (amd) allows the CPU's to communicate with eachother at cpu speeds, whereas the shared cache (intel), although addressable by both chips, is controlled by cpu instructions which are communicated over the FSB. This significantly improves intel core-to-core data transfer speeds (as the cache-stored data won't go over the FSB) but those chip-to-ship instructions are still relatively slowed.

Real-world, you see that intel is able to match AMD's performance with ever-increasing cache sizes, but that increases die size, decreasing yeild, and increasing price. I'd hoped that AMD had a magic bullet up their sleeve that would allow them to bypass this path, and they've held out quite a while. Hopefully the move to 65nm will offset any extra costs and provide overall benefit to the consumer.


RE: Clock and Cache
By coldpower27 on 3/14/2006 7:26:56 PM , Rating: 2

Well Conroe being on 65nm has a die size of ~ 145mm2 somewhere around this range, so basically about on level with the 90nm Manchester Athlon64x2 Core, also keep in mind Intel has better cache densities then AMD for the most part and hence was able to put on quite a bit of cache on their processor.

On the other hand the move to Socket AM2 processor has increased the die to 220mm2 for the 2x1MB parts the Windsor core.

Intel is selling this CPU for 316US and higher though so I think they will make quite a bit on this core, while they have a ~ 11xmm2 Allendale 2MB cache core for the 241US and 209US price points.

If AMD just shrinks the Windsor core to 65nm the die size will reduce to 132mm2, which is a tad smaller then Conroe but larger then Allendale.


RE: Clock and Cache
By Viditor on 3/15/2006 6:31:55 AM , Rating: 2
quote:
also keep in mind Intel has better cache densities then AMD for the most part and hence was able to put on quite a bit of cache on their processor

Good point, but remember that AMD licensed Z-Ram for cache at the end of last year. Z-Ram has a density which is 5 times that of their current cache, and runs at a FAR lower power level.


RE: Clock and Cache
By coldpower27 on 3/15/2006 7:28:06 AM , Rating: 2
On this you will have to accept my skepticism until AMD releases a product with vastly superior caches densities then the cache used in Windsor.


RE: Clock and Cache
By Viditor on 3/15/2006 8:31:32 AM , Rating: 2
Skepticism noted and accepted...but may I ask why?


RE: Clock and Cache
By coldpower27 on 3/15/2006 2:32:16 PM , Rating: 2
Simple AMD and Intel both talk about how great their future products and processes are. In AMD's case I heave heard something about 40% better transistor performance compared to a generic 65nm process and that Z-RAM tech about 5 times better cache desnity, without a shred of evidence to back this up jsut their word.

Conroe is a different story however, that as we know is a good product without a doubt.

As always just because they have access to this doesn't mean it will be implemented that quickly, if and when AMD improves their cache densities in an actual product and not just hype some tech that they had acquired is when I will believe they can increase their cache densities.

For the moment their cache density will remain inferior at least until they move to the 65nm process. Though cache desnity has already been improved on the Windsor core Athlon64x2.



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