Henri Richard Confirms K8L CPU Core, Some Details
March 14, 2006 2:40 PM
comment(s) - last by
In a recent interview, AMD's next generation CPU architecture gets a name and a socket
Digitimes has a
to its interview with AMD's Henri Richard. We covered the first
interview here yesterday
. Digitimes tried to squeeze a few more details out of Richard about the upcoming K8L platform architecture. In the first interview, Richard would not comment on K8L.
That's not to say we're going to present K8L at Computex – don't get me wrong – but I think that that would be a good time to start to disclose more about the future because one of the strong attributes of our roadmap, both in 2006 and 2007, is socket compatibility. The nice thing we're going to do is to deliver to customers. Whatever improvements K8L will provide, they will be applicable to some of the sockets we will be introducing. Therefore, there's a certain logic, to my mind, in disclosing more at that time.
In the first interview, Richard referred to the new architecture as "8KL" instead, but Digitimes reporters did not get back to us about this idiosyncrasy. The three sockets AMD has on the roadmap are the
1207 pin LGA Socket F for servers
for the desktop and
for mobile devices. All three are expected to have working samples on June 6th, 2006 according to AMD's most recent roadmap.
In response to the approach AMD will take with K8L, Richard previously claimed that
future AMD micro-architectures are strictly evolutionary and not revolutionary
. In yesterday's interview, he also claimed that AMD will arrive at better performance by improving clock speeds and increasing cache sizes, but that future core technologies will have increased integer and floating-point performance. Seeing as K8L is the only technology on the AMD roadmap for the next year or so after AM2, we can only speculate as to what Richard means by that statement.
Chris Hall from Digitimes has confirmed with us that the "8KL" reference was a misquote and that Richard was really referring to K8L.
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RE: Clock and Cache
3/14/2006 3:44:30 PM
You mean the one that has been used for the last 30 years? Ohnoes, how shameful!
It could be because it actually works. The problem is only when you rely solely on that trick, with a chip that doesn't scale well enough.
It's literally the oldest trick in the book. And the reason is that it *always* works. Dualcore chips only help if you run multithreaded apps. Onboard FPU's only work if you have lots of FP operations. Pipelining only works when you have dependencies spred out sufficiently, and out of order execution works, but at the expense of a lot of die space. (and is sorta already included). But if you raise the clock speed, you get better performance, period. (Assuming of course you don't reduce the efficiency of any other parts of the chip)
If they've got an architecture that can scale to higher clock speeds, they'd be dumb not to use it. If they've got a small core compared to Intel's, why not use that extra space for more cache?
RE: Clock and Cache
3/14/2006 7:02:42 PM
I agree, and with the onboard memory controller, it may work better than ever (seeing as intel's answer to the on-board controller is to increase cache size). I've wondered long and hard about why AMD hasn't scaled their cpu's up faster and harder, and why they havent used all that extra die space. I guess the real reason was marketing!
They only need to be faster by enough of a margin to be better, but with k8 and Core both basically ancestors of the PIII, and Core being the *presumably* better of the two, will K8L be enough of an evolution to hold AMD in the race until their next architecture refresh (especially with Intel scaling their Core speeds to fast?)
Im ecstatic that intel is back in the game, because that means AMD needs to start thinking again, but it worries me that this could be their best response.
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