Hello AMD Socket G34
July 16, 2008 5:38 PM
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AMD's 12-core and 8-core processors get a new home in 2010
AMD's newest roadmap reveals a major shift in early 2010: the company will once again overhaul its socket architecture to make way for DDR3 support.
The new socket, dubbed G34, will also ship with two new second-generation 45nm processors. The first of these processors, 8-core
, is described as a "twin native-quadcore
processor" by one AMD engineer.
, expected to ship late this year, is AMD's first 45nm shrink of the ill-fated
This past April,
AMD guidance hinted at a 12-core behemoth of a processor
. This CPU is now named
after the French town made famous by its Formula One French Grand Prix circuit.
Both of these new processors will feature four HyperTransport 3 interconnects, 12MB of L3 cache and 512KB L2 cache per core.
chip, scheduled for launch late this year
but already well leaked
, is the first to feature tri-channel DDR3 memory support. AMD will up the ante in 2010, with registered and unregistered quad-channel DDR3 support. Current roadmaps claim standard support will include speeds from 800 to 1600 MHz.
AMD insiders would reveal very little about the G34 socket, other than its a derivative of the highly secretive G3 socket that was to replace Socket F (1207). As far as company documentation goes, G3 ceased to exist in March 2008, and has been replaced with the G34 program instead. The first of these sockets will be available for developers in early 2009.
We counted 1974 pin connects on the leaked G34 diagram -- 767 more pins than AMD's current LGA1207 socket. Given the additional interconnect pathways for DDR3 and the HyperTransport buses, a significant increase in the number of pins was to be expected.
The addition of a fourth HyperTransport link may prove to be one of the most interesting features of the
processors. In a full four-socket configuration, each physical processor will dedicate a HyperTransport link to each of the other sockets. This leaves one additional HyperTransport lane per processor, which AMD documentation claims will finally be used for its
The hype behind
largely disappeared after AMD's
launch sour, though the company has hinted before that
will make a perfect interconnect to GPUs or IBM Cell processors. This is exactly the type of setup roadmapped for the fastest public supercomputer in the world,
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7/17/2008 7:21:59 AM
Phonetically it is "Many Cour" :-)
7/17/2008 11:06:01 AM
Actually more in the lines of Mannee Coor.
It's really hard to translate phonetics from Latin based languages which have one unique sound for each vowel (though it may be made shorter or longer) to English, in which the same vowel usually has a different sound depending on its position and even then there are many exceptions.
That's the bothersome thing about English... But anyway it's a far more practical language than those derived from Latin, to the point that I always prefer reading technical material in English rather than in my own language.
7/17/2008 1:49:25 PM
Ah, you mean manicure?
So this new chip will just look pretty in its new socket?
(for the record, I think "many cores" is the best fitting sound-alike)
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