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  (Source: AMD)
AMD's 12-core and 8-core processors get a new home in 2010

AMD's newest roadmap reveals a major shift in early 2010: the company will once again overhaul its socket architecture to make way for DDR3 support. 

The new socket, dubbed G34, will also ship with two new second-generation 45nm processors. The first of these processors, 8-core Sao Paolo, is described as a "twin native-quadcore Shanghai processor" by one AMD engineer.  Shanghai, expected to ship late this year, is AMD's first 45nm shrink of the ill-fated Barcelona processor. 

This past April, AMD guidance hinted at a 12-core behemoth of a processor.  This CPU is now named Magny-Cours after the French town made famous by its Formula One French Grand Prix circuit. 

Both of these new processors will feature four HyperTransport 3 interconnects, 12MB of L3 cache and 512KB L2 cache per core.

Intel's next-generation Nehalem chip, scheduled for launch late this year but already well leaked, is the first to feature tri-channel DDR3 memory support.  AMD will up the ante in 2010, with registered and unregistered quad-channel DDR3 support.  Current roadmaps claim standard support will include speeds from 800 to 1600 MHz.

AMD insiders would reveal very little about the G34 socket, other than its a derivative of the highly secretive G3 socket that was to replace Socket F (1207). As far as company documentation goes, G3 ceased to exist in March 2008, and has been replaced with the G34 program instead.  The first of these sockets will be available for developers in early 2009.

We counted 1974 pin connects on the leaked G34 diagram -- 767 more pins than AMD's current LGA1207 socket.  Given the additional interconnect pathways for DDR3 and the HyperTransport buses, a significant increase in the number of pins was to be expected.

The addition of a fourth HyperTransport link may prove to be one of the most interesting features of the Sao Paulo and Magny-Cours processors. In a full four-socket configuration, each physical processor will dedicate a HyperTransport link to each of the other sockets. This leaves one additional HyperTransport lane per processor, which AMD documentation claims will finally be used for its long-discussed Torrenza program.

The hype behind Torrenza largely disappeared after AMD's Barcelona launch sour, though the company has hinted before that Torrenza will make a perfect interconnect to GPUs or IBM Cell processors.  This is exactly the type of setup roadmapped for the fastest public supercomputer in the world, IBM's Roadrunner.


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Are these Shanghai K10 CPUs?
By phatboye on 7/17/2008 3:40:28 AM , Rating: 2
Are the CPUs in this article K10 or is this based off the new bulldozer cores?




By KristopherKubicki (blog) on 7/17/2008 1:39:49 PM , Rating: 1
Yes, these are all K10


RE: Are these Shanghai K10 CPUs?
By vsary6968 on 7/17/2008 11:11:13 PM , Rating: 1
It base on K10.5 success.But the Shanghai will have HT 3.0 interconnect.This HT 3.0 is way faster than the HT 1.0 from Barcelona.I assume that K10.5 is about 10-30% faster than the K10.This is only my opinion.Not to include Deneb.I don't think Deneb will perform wll until Q1 2009. Because the K10.5 Hydra will be out with 1mb of L2 cache per core and L3 of 6mb.I'm not sure if the K10.5 Hydra is the Deneb FX or not.So, this one will be the real competition to Nehalem.


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