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  (Source: AMD)
AMD's 12-core and 8-core processors get a new home in 2010

AMD's newest roadmap reveals a major shift in early 2010: the company will once again overhaul its socket architecture to make way for DDR3 support. 

The new socket, dubbed G34, will also ship with two new second-generation 45nm processors. The first of these processors, 8-core Sao Paolo, is described as a "twin native-quadcore Shanghai processor" by one AMD engineer.  Shanghai, expected to ship late this year, is AMD's first 45nm shrink of the ill-fated Barcelona processor. 

This past April, AMD guidance hinted at a 12-core behemoth of a processor.  This CPU is now named Magny-Cours after the French town made famous by its Formula One French Grand Prix circuit. 

Both of these new processors will feature four HyperTransport 3 interconnects, 12MB of L3 cache and 512KB L2 cache per core.

Intel's next-generation Nehalem chip, scheduled for launch late this year but already well leaked, is the first to feature tri-channel DDR3 memory support.  AMD will up the ante in 2010, with registered and unregistered quad-channel DDR3 support.  Current roadmaps claim standard support will include speeds from 800 to 1600 MHz.

AMD insiders would reveal very little about the G34 socket, other than its a derivative of the highly secretive G3 socket that was to replace Socket F (1207). As far as company documentation goes, G3 ceased to exist in March 2008, and has been replaced with the G34 program instead.  The first of these sockets will be available for developers in early 2009.

We counted 1974 pin connects on the leaked G34 diagram -- 767 more pins than AMD's current LGA1207 socket.  Given the additional interconnect pathways for DDR3 and the HyperTransport buses, a significant increase in the number of pins was to be expected.

The addition of a fourth HyperTransport link may prove to be one of the most interesting features of the Sao Paulo and Magny-Cours processors. In a full four-socket configuration, each physical processor will dedicate a HyperTransport link to each of the other sockets. This leaves one additional HyperTransport lane per processor, which AMD documentation claims will finally be used for its long-discussed Torrenza program.

The hype behind Torrenza largely disappeared after AMD's Barcelona launch sour, though the company has hinted before that Torrenza will make a perfect interconnect to GPUs or IBM Cell processors.  This is exactly the type of setup roadmapped for the fastest public supercomputer in the world, IBM's Roadrunner.

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RE: "twin native-quadcore Shanghai processor"
By Parhel on 7/16/2008 10:39:39 PM , Rating: 2
Remember cornfedone? You know, that guy who, before Phenom was released, used to come here bitching about how Intel's quad-cores were so inferior and calling them "glue-blob?" And then trying to pretend that "glue-blob" was something that people in the industry were calling it? I wonder what he is doing right now?

RE: "twin native-quadcore Shanghai processor"
By Crassus on 7/17/2008 12:58:20 AM , Rating: 2
Unfortunately, yes. If I remember correctly, I even remember that he used to be Beenthere or something like that. I suppose he's grown up in the meantime. One can't stay 13 forever :)

By johnsonx on 7/19/2008 4:35:40 PM , Rating: 2
Cornfedone and Beenthere both posted in the same time period. You may be thinking one or both of them used to be the famus Cramitpal. Myself, I once posed a slightly different theory:

RE: "twin native-quadcore Shanghai processor"
By psychobriggsy on 7/17/2008 5:45:24 AM , Rating: 2
To be fair, the Intel dual-die system did share the single front side bus, which did lead to some compromises. I think they now use a dedicated interconnect between the cores, but don't quote me on that, it just seems a logical thing to implement to enable high FSB speeds and reduce contention.

AMD would connect them with HyperTransport, which is a little bit more elegant (mainly because it isn't a shared bus though). On the other hand having working dual-die quad-core CPUs is more elegant than not having native quad-core CPUs!

Do these CPUs also have a PCIe bus on board? If they want to use all 4 HT3 links to talk to other CPUs and Torrenza GPUs/Cells then they'll need an interconnect to the rest of the system as well.

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