backtop


Print 94 comment(s) - last by SiliconJon.. on Jul 22 at 7:49 PM


  (Source: AMD)
AMD's 12-core and 8-core processors get a new home in 2010

AMD's newest roadmap reveals a major shift in early 2010: the company will once again overhaul its socket architecture to make way for DDR3 support. 

The new socket, dubbed G34, will also ship with two new second-generation 45nm processors. The first of these processors, 8-core Sao Paolo, is described as a "twin native-quadcore Shanghai processor" by one AMD engineer.  Shanghai, expected to ship late this year, is AMD's first 45nm shrink of the ill-fated Barcelona processor. 

This past April, AMD guidance hinted at a 12-core behemoth of a processor.  This CPU is now named Magny-Cours after the French town made famous by its Formula One French Grand Prix circuit. 

Both of these new processors will feature four HyperTransport 3 interconnects, 12MB of L3 cache and 512KB L2 cache per core.

Intel's next-generation Nehalem chip, scheduled for launch late this year but already well leaked, is the first to feature tri-channel DDR3 memory support.  AMD will up the ante in 2010, with registered and unregistered quad-channel DDR3 support.  Current roadmaps claim standard support will include speeds from 800 to 1600 MHz.

AMD insiders would reveal very little about the G34 socket, other than its a derivative of the highly secretive G3 socket that was to replace Socket F (1207). As far as company documentation goes, G3 ceased to exist in March 2008, and has been replaced with the G34 program instead.  The first of these sockets will be available for developers in early 2009.

We counted 1974 pin connects on the leaked G34 diagram -- 767 more pins than AMD's current LGA1207 socket.  Given the additional interconnect pathways for DDR3 and the HyperTransport buses, a significant increase in the number of pins was to be expected.

The addition of a fourth HyperTransport link may prove to be one of the most interesting features of the Sao Paulo and Magny-Cours processors. In a full four-socket configuration, each physical processor will dedicate a HyperTransport link to each of the other sockets. This leaves one additional HyperTransport lane per processor, which AMD documentation claims will finally be used for its long-discussed Torrenza program.

The hype behind Torrenza largely disappeared after AMD's Barcelona launch sour, though the company has hinted before that Torrenza will make a perfect interconnect to GPUs or IBM Cell processors.  This is exactly the type of setup roadmapped for the fastest public supercomputer in the world, IBM's Roadrunner.


Comments     Threshold


This article is over a month old, voting and posting comments is disabled

By Master Kenobi (blog) on 7/16/2008 7:55:57 PM , Rating: 0
This is going to rape their fab process. Given the size of what needs to fit in that socket chances are that defects will be high (resulting in unusable silicon) and that the costs will be high (thats alot of wafer space). I believe Intel will shrink to 32nm when it moves to the 8 and 12 core processors (wise move).


By masher2 (blog) on 7/16/2008 8:35:18 PM , Rating: 5
Socket size is dependent on pin count, not die area. The 8-core Sao Paolo should be no larger than AMD's current quad-core offerings.


By Warren21 on 7/17/2008 12:39:00 AM , Rating: 3
We have a winner.

Socket size is only determined by the package size, which like Masher pointed out, is dependant on pincount.


RE: Am I seeing a retangular processor socket......?
By Arc 0V on 7/17/2008 1:20:52 AM , Rating: 2
Nehalem processors are a bit rectangular too. I really hope these AMD processors are on par with Intel's current offerings at that time, so more new innovations get pushed regardless of who does them for less money. Yay for the consumer!


RE: Am I seeing a retangular processor socket......?
By Targon on 7/17/08, Rating: 0
By Master Kenobi (blog) on 7/17/2008 9:32:36 AM , Rating: 2
Likely won't happen like that again. With Nehalem, Intel has leveled off the playing field. QuickPath is similar to Hypertransport (although QuickPath is faster than HT3.0). Intel has also added the IMC just as AMD has. This should nix any real advantages AMD might gain by changing architecture around since all things are relatively equal in terms of architecture now.


By vsary6968 on 7/21/2008 6:44:23 AM , Rating: 2
Which information did get it from that Quickpath is faster than HT3.0? Because AMD HT3.0 haven't work on any Barcelona CPU yet.Current Barcelona current CPU only use HT1.0 and HT2.0. But AMD working on to succeed the HT3.0 in Shanghai processor.As the current processor only the Phenom CPU have HT3.0. Shanghai 45nm not only the cache is improving, it also improve it single thread is improving 15 percent faster than current processor clock for clock.


By Risforrocket on 7/22/2008 5:53:42 PM , Rating: 2
Socket size, pfft. It's not the size that counts, it's the throughput.


By DeepBlue1975 on 7/17/2008 11:14:19 AM , Rating: 2
The article suggests that their 8 core processor will be nothing more than 2 of their quad core chips put into the same package, something that doesn't affect the yields. Besides, those quad cores are supposed to be based on the 45nm revision of Barcelona (Shangai).

I hope they can make Shangai fast enough to compete with Nehalem, but I know that might be to much to ask from a Barcelona refresh.


By vsary6968 on 7/17/2008 11:20:57 PM , Rating: 2
I think Shanghai will compete with Nehalem head to head with the Hypertransport 3.0 versus QPI.Shanghai will release In October or November.But not in big volume.We have to wait to see who will be the true king of cpu.

But 2010 will have K11 Bulldozer.


By William Gaatjes on 7/17/2008 11:58:27 AM , Rating: 3
From the news :

quote:
The first of these processors, 8-core Sao Paolo, is described as a "twin native-quadcore Shanghai processor" by one AMD engineer.


I would think AMD is going to place 2 quadcore in 1 package.

Hypertransport would be fast enough for it.

And quad memory channel reads to me as 2x dualchannel.

That is when i read the text.

Would not be a bad move to start with and then go native 8 cores later.


By William Gaatjes on 7/17/2008 11:59:52 AM , Rating: 2
Woops deepblue beat me to it.


By Master Kenobi (blog) on 7/18/2008 7:59:34 AM , Rating: 1
quote:
And quad memory channel reads to me as 2x dualchannel.

This means that the memory banks will be dedicated to specific cores. Thats likely going to suck if the DIMM's need to feed data to processing cores on the other path, leading to increased latency. Granted HT3.0 is fast, but still this will put a damper on it to some extent.


"Intel is investing heavily (think gazillions of dollars and bazillions of engineering man hours) in resources to create an Intel host controllers spec in order to speed time to market of the USB 3.0 technology." -- Intel blogger Nick Knupffer














botimage
Copyright 2014 DailyTech LLC. - RSS Feed | Advertise | About Us | Ethics | FAQ | Terms, Conditions & Privacy Information | Kristopher Kubicki