quote: SMT (let's call it by it's proper name) will help a great deal. This CPU has 4 execution units that need to be kept fed. SMT will do a great deal to keep those units running
quote: 2. You have just proven MY point...Conroe has 4 ALUs! The fewer execution units you have, the more important it is that each is more efficient. Conroe has double the execution units of Netburst, which means that the stalled ALU will not effect the work done to anywhere near the degree that it would on the Netburst architecture. Athlon has 3 execution units, and SMT was found to be more of a hindrance than a help on the Athlon architecture...imagine what the effect would be on 4.
quote: SMT isn't implemented just because of stalls. The more execution units you have, the harder is to keep them fed using only one thread. That's why Power5, which issue 8 instructions and execute 5 per cycle, has SMT
quote: The number escapes me.. but 15 pipelines?? (A64) is a lot easier to recover from than having to flush out 31 different stages (P4 Prescott) I don't see why Conroe which is based on Pentium M as we all know (~15 pipes) would benefit from HT.
quote: Good luck to AMD finding four adjacent cores all operating at the same speed and TDP with minimal defects
quote: Furthermore, each pair is using a shared cache which is superior to even AMD's point connections
quote: if it works AND Intel prices it reasonable, I can live it
quote: Thanks to cache partitioning coherency mostly becomes a non-issue
quote: Your first false assumtion is that both L2 caches must always be coherent
quote: You have been very skillful in taking a P4 argument and applying it to Conroe. Of course they fall apart because you don't know the Conroe architechure
quote: This, folks, you why you should make sure your children stay in school