Dodeca-core: The Megahertz Race is Now Officially the Multi-core Race
April 17, 2008 6:51 PM
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AMD engineers reveal details about the company's upcoming 45nm processor roadmap, including plans for 12-core processors
" the reporters cry during the AMD's financial analyst day today. Despite the fact that the company will lay off nearly 5% of its work force this week, followed by another 5% next month, most employees interviewed by
continue to convey an optimistic outlook.
The next major milestone for the CPU engineers comes late this year, with the debut of 45nm
, for all intents and purposes, is nearly identical to
the B3 stepping of Socket 1207 Opteron (
) shipping today
. However, where as
had its HyperTransport 3.0 clock generator fused off,
will once again attempt to get HT3.0 right.
Original roadmaps anticipated that HT3.0 would be used for socket-to-socket communication, but also for communication to the Southbridge controllers. Motherboard manufacturers have confirmed that this is no longer the case, and that HT3.0 will only be used for inter-CPU communication.
"Don't be disappointed, AMD is making up for it," hints one engineer. Further conversations revealed that inter-CPU communication is going to be a big deal with the 45nm refresh. The first breadcrumb comes with a new "native six-core"
derivative, currently codenamed
. This processor is clearly targeted at
Intel's recently announced six-core, 45nm
But sextuple-core processors have been done, or at least we'll see the first ones this year. The real neat stuff comes a few months after, where AMD will finally ditch the "native-core" rhetoric. Two separate reports sent to
from AMD partners indicate that Shanghai and its derivatives will also get twin-die per package treatment.
AMD planned twin-die configurations
as far back as the K8 architecture
, though abandoned those efforts. The company never explained why those processors were nixed, but just weeks later "native quad-core" became a major marketing campaign for AMD in anticipation of
processor could enable 12 cores in a single package. Each of these cores will communicate to each other via the now-enabled HT3.0 interconnect on the processor.
The rabbit hole gets deeper. Since each of these processors will contain a dual-channel memory controller, a single-core can emulate quad-channel memory functions by accessing the other dual-channel memory controller on the same socket. This move is likely a preemptive strike against
tri-channel memory controller
Motherboard manufacturers claim
and its many-core derivatives will be backwards compatible with existing Socket 1207 motherboards. However, processor-to-processor communication will downgrade to lower HyperTransport frequencies on these older motherboards. The newest 1207+ motherboards will officially support the HyperTransport 3.0 frequencies.
is currently taped out and running Windows at AMD.
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RE: what kind of learning curve is there for 12 core programs?
4/18/2008 9:45:54 AM
You're technically right, but the performance hit is very slight. But there are also times where the address space from a 64 bit Windows OS will cause a 32 bit program to run faster.
See, in most cases under a 32 bit OS, your program is limited to 2GB ram. There's a flag you can set, if the program is written for it, to extend that to 3GB. However, under a 64 bit Windows OS, each 32 bit app can have 4GB of unfettered address space. If you've got more than 2GB of RAM and a memory 32 bit hungry app, the odds are good you'll run faster on 64 bit OS despite the very minor hit from the 32-to-64 translation layer.
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