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AMD engineers reveal details about the company's upcoming 45nm processor roadmap, including plans for 12-core processors





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About the memory controllers
By TeXWiller on 4/17/2008 8:47:10 PM , Rating: 2
quote:
The rabbit hole gets deeper. Since each of these processors will contain a dual-channel memory controller, a single-core can emulate quad-channel memory functions by accessing the other dual-channel memory controller on the same socket. This move is likely a preemptive strike against Intel's Nehalem tri-channel memory controller.
See AMD BIOS and Kernel Developer’s Guide, revision 3.06, page 13, the overview section. AMD is promising 3 DDR3 interfaces (channels) which would be quite a nice match for the coming six-core Shanghai derivative. Nehalem and Shanghai would have equal memory bandwith.




By KristopherKubicki on 4/17/2008 9:29:12 PM , Rating: 2
Yeah, looks like conflicting info for now. I'll try to confirm.


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