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AMD engineers reveal details about the company's upcoming 45nm processor roadmap, including plans for 12-core processors

"Shanghai! Shanghai!" the reporters cry during the AMD's financial analyst day today. Despite the fact that the company will lay off nearly 5% of its work force this week, followed by another 5% next month, most employees interviewed by DailyTech continue to convey an optimistic outlook.

The next major milestone for the CPU engineers comes late this year, with the debut of 45nm Shanghai. Shanghai, for all intents and purposes, is nearly identical to the B3 stepping of Socket 1207 Opteron (Barcelona) shipping today.  However, where as Barcelona had its HyperTransport 3.0 clock generator fused off, Shanghai will once again attempt to get HT3.0 right.

Original roadmaps anticipated that HT3.0 would be used for socket-to-socket communication, but also for communication to the Southbridge controllers. Motherboard manufacturers have confirmed that this is no longer the case, and that HT3.0 will only be used for inter-CPU communication.

"Don't be disappointed, AMD is making up for it," hints one engineer.  Further conversations revealed that inter-CPU communication is going to be a big deal with the 45nm refresh.  The first breadcrumb comes with a new "native six-core" Shanghai derivative, currently codenamed Istanbul.  This processor is clearly targeted at Intel's recently announced six-core, 45nm Dunnington processor.

But sextuple-core processors have been done, or at least we'll see the first ones this year.  The real neat stuff comes a few months after, where AMD will finally ditch the "native-core" rhetoric.  Two separate reports sent to DailyTech from AMD partners indicate that Shanghai and its derivatives will also get twin-die per package treatment.  

AMD planned twin-die configurations as far back as the K8 architecture, though abandoned those efforts.  The company never explained why those processors were nixed, but just weeks later "native quad-core" became a major marketing campaign for AMD in anticipation of Barcelona.

A twin-die Istanbul processor could enable 12 cores in a single package. Each of these cores will communicate to each other via the now-enabled HT3.0 interconnect on the processor.  

The rabbit hole gets deeper.  Since each of these processors will contain a dual-channel memory controller, a single-core can emulate quad-channel memory functions by accessing the other dual-channel memory controller on the same socket.  This move is likely a preemptive strike against Intel's Nehalem tri-channel memory controller.
 
Motherboard manufacturers claim Shanghai and its many-core derivatives will be backwards compatible with existing Socket 1207 motherboards.  However, processor-to-processor communication will downgrade to lower HyperTransport frequencies on these older motherboards. The newest 1207+ motherboards will officially support the HyperTransport 3.0 frequencies.

Shanghai is currently taped out and running Windows at AMD.


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K10 cores?
By MikeMurphy on 4/17/2008 7:19:38 PM , Rating: 3
Fast interconnects are great but this is like putting spinners on a civic until the K10 core gets replaced or can clock competitively.




RE: K10 cores?
By Zurtex on 4/17/2008 7:35:48 PM , Rating: 3
It's very good for certain server application and fantastic for super computers. If they want to stay ahead of Intel's next-gen cores in the super computer market (Core2s aren't even worth considering because of their low bandwidth) they need more cores and higher bandwidth.


RE: K10 cores?
By kkwst2 on 4/17/2008 10:28:46 PM , Rating: 2
First, see my post above. That's just not true for many applications. The quad Opteron still scales quite favorably for many HPC applications.

Second, that's a horrible analogy. Putting spinners on anything is pointless. They would look just as silly on a Corvette as they would on a Civic.

The FSB limits scaling on the Quad core Xeon architecture right now. They're going to on-die memory controllers with Nehalem to solve this. The K10 Opteron is no civic and HT3.0 is not a stupid, pointless accessory.


RE: K10 cores?
By ninjit on 4/18/2008 3:36:46 AM , Rating: 1
quote:
Fast interconnects are great but this is like putting spinners on a civic until the K10 core gets replaced or can clock competitively.


Your analogy makes no sense at all. (spinners are useless no matter what you put them on)

If you MUST have a car-related jab at this, think of installing a high-end gearbox in the civic, capable of handling 8k rpm and over 500 lb-ft of torque (or "twist" if you prefer), but not replacing the engine (4k rpm and 128 lb-ft of torque).

But getting back to CPUs... my understanding is that the HT3 link is used to interconnect the 2 dies. Each die has 6 cores which will likely by hooked together via shared cache.

So you actually have 6 K10 cores filling the HT3 link, as opposed to the one - which seems like it should make much better use of the bandwidth.


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