Intel's Core architecture bullets
Intel releases details on its Core architecture

At today’s Intel Developer Forum keynote, Intel’s CTO Justin Rattner announced that the Core architecture has four issue execution with a fourteen stage pipeline. Rattner focused on five new technologies that will make Core different than previous architectures like Netburst. The wider issue execution was obviously the first and most important announcement. However, Conroe will also feature a new 128-bit SSE optimization that will allow all SSE instructions to be completed in a single cycle.

Furthermore, Rattner announced that Core architecture will have micro-ops fusion (already present on all modern Intel processors), but that the new architecture will also include macro-ops fusion. Essentially, macro-ops fusion takes multiple high level instructions, and combines them into a single instruction. For example a “compare” and “jump” instruction can be combined into a single operation.

As we already disclosed, Core will feature shared L2 cache for all of the next generation processors – including the quad core Kentsfield/Clovertown and dual core Conroe/Merom. Intel has completely redesigned the scheduler to prevent collisions with the added bonus that advanced memory management leaves the door open to advanced gating techniques; Intel’s last important point for the Core architecture.

In a nutshell, the new gating techniques will dynamically power certain portions of the CPU on and off on the fly. Intel’s Yonah already had techniques to power off portions of the cache when not in use, but the new gating techniques on Core seem to go above and beyond just powering cache.

"Nowadays you can buy a CPU cheaper than the CPU fan." -- Unnamed AMD executive

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