Print 4 comment(s) - last by Clauzii.. on Mar 8 at 12:41 PM

We haven't been at IDF more than 10 minutes and we've already got block diagrams

As soon as we got to the Spring Intel Developer Forum 2006, Intel gave us exclusive access to the Conroe block diagram before the keynote.  As expected, Conroe uses a shared L2 cache with independent L1 caches per core. 

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Not to brag or anything...
By Shadowmage on 3/7/2006 11:58:40 AM , Rating: 2
... but LaptopLogic got die diagrams way before the show even started ;)

RE: Not to brag or anything...
By JackPack on 3/7/2006 12:34:52 PM , Rating: 2
Of course. Intel uploaded the files yesterday.

By Merovingian on 3/7/2006 8:10:44 PM , Rating: 2
Can someone please explain this? Just curious!

By Clauzii on 3/8/2006 12:41:25 PM , Rating: 2
Looks like intel put in a third ALU per core. That should give some ekstra speed.

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