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An document consistent with Intel roadmaps details the company's upcoming 6-core processor

The same slide deck details side-by-side projections of Nehalem with other AMD and Intel processors

George Out estimates the floating point point and integer performance by extrapolating datapoints on the slid  (Source: ZDNet)
Sun confirms what Intel has been dying to tell us, at least off the record

Late last month in Austria, Intel presented Sun with roadmaps discussing details of its upcoming server platforms, including the fairly secret Xeon Dunnington and Nehalem architectures. Unfortunately for some, this presentation ended up on Sun's public web server over the weekend.

Dunnington, Intel's 45nm six-core Xeon processor from the Penryn family, will succeed the Xeon Tigerton processor.  Whereas Tigerton is essentially two 65nm Core 2 Duo processors fused on one package, Dunnington will be Intel's first Core 2 Duo processor with three dual-core banks. 

Dunnington includes 16MB of L3 cache shared by all six processors. Each pair of cores can also access 3MB of local L2 cache.  The end result is a design very similar to the AMD Barcelona quad-core processor; however, each Barcelona core contains 512KB L2 cache, whereas Dunnington cores share L2 cache in pairs.

To sweeten the deal, all Dunnington processors will be pin-compatible with Intel Tigerton processors, and work with the existing Clarksboro chipset.  Intel's slide claims this processor will launch in the second half of 2008 -- a figure consistent with previous roadmaps from the company.

The leaked slide deck also includes more information about Intel's Penryn successor, codenamed NehalemNehalem is everything Penryn is -- 45nm, SSE4, quad-core -- and then some.  For starters, Intel will abandon the front-side bus model in favor of QuickPath Interconnect; a serial bus similar to HyperTransport.

Perhaps the most ambitious aspect of Nehalem? For the first time in 18 years Intel will pair its processors cores up with on-die memory controllers.  AMD made the switch to on-die memory controllers in 2003. For the next three years its processors were almost unmatched by Intel's offerings.  The on-die memory controller can't come a moment too soon. Intel will also roll out tri-channel DDR3 with the Nehalem, and all that extra bandwidth can only be put to use if there are no bottlenecks.

As noted by ZDNet blogger George Ou, the slides contain some rudimentry benchmarks for Nehalem and other publicly available processors.  From this slide deck, Ou estimates Nehalem's SPEC*fp_rate_base2006 at 163 and the SPEC*int_rate_base2006 at 176.  By contrast, Intel's fastest Harpertown Xeon X5482 pulls a measly 80 and 122 SPEC fp and int rate_base2006.

The Nehalem processor more than doubles the floating point performance of its current Penryn-family processors.  Ou adds, "We’ll most likely know by the end of this year what the actual scores are, but I doubt they will be more than 5% to 10% off from these estimated projections."

It's important to note that these estimates are not actual benchmarks.  Intel's document states, "Projections based on *SPECcpu2006 using dual socket Intel Xeon 5160 Processor performance as the baseline." As discussed on DailyTech before, simulated benchmarks offer little substance in favor of the real deal.

As of February 2008, the company plans to launch Nehalem in Q4 2008.

Sun has since removed the slide deck from its website.


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RE: On-die memory controller?
By rninneman on 2/25/2008 1:13:14 PM , Rating: 1
The FSB bottleneck is mostly AMD marketing. There is no desktop application that can saturate the FSB on current Intel platforms. The K8 owned the P4 because it was a more efficient core. Only certain specific server workloads benefit from the ODMC. No Intel product yet has an ODMC and they still own everything AMD makes including Barcelona.


RE: On-die memory controller?
By fic2 on 2/25/2008 6:29:25 PM , Rating: 3
Intel made up for the lack of an on-die memory controller by putting HUGE amounts of cache on the chip. With an on-die memory controller they can probably cut this back quite a bit and possibly save die space making the chip size/cost less and lower heat. Of course, this is assuming that the die space used for the on-die memory controller is less than the cache.


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