Sun Leaks 6-core Intel Xeon, Nehalem Details
February 25, 2008 3:11 AM
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An document consistent with Intel roadmaps details the company's upcoming 6-core processor
The same slide deck details side-by-side projections of Nehalem with other AMD and Intel processors
George Out estimates the floating point point and integer performance by extrapolating datapoints on the slid
Sun confirms what Intel has been dying to tell us, at least off the record
Late last month in Austria, Intel presented Sun with roadmaps discussing details of its upcoming server platforms, including the fairly secret Xeon
architectures. Unfortunately for some, this presentation ended up on Sun's public web server over the weekend.
, Intel's 45nm six-core Xeon processor from the
family, will succeed the Xeon
is essentially two 65nm Core 2 Duo processors fused on one package,
will be Intel's first Core 2 Duo processor with three dual-core banks.
includes 16MB of L3 cache shared by all six processors. Each pair of cores can also access 3MB of local L2 cache. The end result is a design very similar to the AMD Barcelona quad-core processor; however, each
core contains 512KB L2 cache, whereas
cores share L2 cache in pairs.
To sweeten the deal, all
processors will be pin-compatible with
, and work with the existing
chipset. Intel's slide claims this processor will launch in the second half of 2008 -- a figure consistent with previous roadmaps from the company.
The leaked slide deck also includes more information about Intel's
is -- 45nm, SSE4, quad-core -- and then some. For starters, Intel will abandon the front-side bus model in favor of QuickPath Interconnect; a serial bus similar to HyperTransport.
Perhaps the most ambitious aspect of Nehalem? For the first time in 18 years Intel will pair its processors cores up with on-die memory controllers. AMD
made the switch to on-die memory controllers in 2003
. For the next three years its processors were almost unmatched by Intel's offerings. The on-die memory controller can't come a moment too soon. Intel will also roll out tri-channel DDR3 with the
, and all that extra bandwidth can only be put to use if there are no bottlenecks.
As noted by
blogger George Ou,
the slides contain some rudimentry benchmarks
and other publicly available processors. From this slide deck, Ou estimates Nehalem's SPEC*fp_rate_base2006 at 163 and the SPEC*int_rate_base2006 at 176. By contrast, Intel's fastest
Xeon X5482 pulls a measly 80 and 122 SPEC fp and int rate_base2006.
processor more than doubles the floating point performance of its current
-family processors. Ou adds, "We’ll most likely know by the end of this year what the actual scores are, but I doubt they will be more than 5% to 10% off from these estimated projections."
It's important to note that these estimates are not actual benchmarks. Intel's document states, "Projections based on *SPECcpu2006 using dual socket Intel Xeon 5160 Processor performance as the baseline." As discussed on
offer little substance in favor of the real deal.
As of February 2008,
the company plans to launch
in Q4 2008
Sun has since removed the slide deck from its website.
This article is over a month old, voting and posting comments is disabled
RE: CST vs HTT
2/25/2008 10:32:31 AM
Simply by virtue of being a point-to-point protocol it is far more similar to HT than to the existing FSB. That's not speculation, it's based on public information, e.g. from Intel, here:
By the way, the legacy acronym you're looking for is CSI.
"Intel is investing heavily (think gazillions of dollars and bazillions of engineering man hours) in resources to create an Intel host controllers spec in order to speed time to market of the USB 3.0 technology." -- Intel blogger Nick Knupffer
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