Sun Leaks 6-core Intel Xeon, Nehalem Details
February 25, 2008 3:11 AM
comment(s) - last by
An document consistent with Intel roadmaps details the company's upcoming 6-core processor
The same slide deck details side-by-side projections of Nehalem with other AMD and Intel processors
George Out estimates the floating point point and integer performance by extrapolating datapoints on the slid
Sun confirms what Intel has been dying to tell us, at least off the record
Late last month in Austria, Intel presented Sun with roadmaps discussing details of its upcoming server platforms, including the fairly secret Xeon
architectures. Unfortunately for some, this presentation ended up on Sun's public web server over the weekend.
, Intel's 45nm six-core Xeon processor from the
family, will succeed the Xeon
is essentially two 65nm Core 2 Duo processors fused on one package,
will be Intel's first Core 2 Duo processor with three dual-core banks.
includes 16MB of L3 cache shared by all six processors. Each pair of cores can also access 3MB of local L2 cache. The end result is a design very similar to the AMD Barcelona quad-core processor; however, each
core contains 512KB L2 cache, whereas
cores share L2 cache in pairs.
To sweeten the deal, all
processors will be pin-compatible with
, and work with the existing
chipset. Intel's slide claims this processor will launch in the second half of 2008 -- a figure consistent with previous roadmaps from the company.
The leaked slide deck also includes more information about Intel's
is -- 45nm, SSE4, quad-core -- and then some. For starters, Intel will abandon the front-side bus model in favor of QuickPath Interconnect; a serial bus similar to HyperTransport.
Perhaps the most ambitious aspect of Nehalem? For the first time in 18 years Intel will pair its processors cores up with on-die memory controllers. AMD
made the switch to on-die memory controllers in 2003
. For the next three years its processors were almost unmatched by Intel's offerings. The on-die memory controller can't come a moment too soon. Intel will also roll out tri-channel DDR3 with the
, and all that extra bandwidth can only be put to use if there are no bottlenecks.
As noted by
blogger George Ou,
the slides contain some rudimentry benchmarks
and other publicly available processors. From this slide deck, Ou estimates Nehalem's SPEC*fp_rate_base2006 at 163 and the SPEC*int_rate_base2006 at 176. By contrast, Intel's fastest
Xeon X5482 pulls a measly 80 and 122 SPEC fp and int rate_base2006.
processor more than doubles the floating point performance of its current
-family processors. Ou adds, "We’ll most likely know by the end of this year what the actual scores are, but I doubt they will be more than 5% to 10% off from these estimated projections."
It's important to note that these estimates are not actual benchmarks. Intel's document states, "Projections based on *SPECcpu2006 using dual socket Intel Xeon 5160 Processor performance as the baseline." As discussed on
offer little substance in favor of the real deal.
As of February 2008,
the company plans to launch
in Q4 2008
Sun has since removed the slide deck from its website.
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RE: On-die memory controller?
2/25/2008 9:05:26 AM
The on-die memory controller was much faster at launch and blew away existing netburst designs that were benching more than double the latency. That blew away the old p4s and the like because it was so much higher. New core2 optimizations have significantly lowered latencies and made their on die controller no longer a significant advantage. If you look here:
The top benchmark was trickery and inaccurate but the second is on par with the usual benchmarks. AMD around 45ns, Intel around 60. 33% sounds like a hefty difference until you realize mem latency is only a small piece of the total memory performance scope.
RE: On-die memory controller?
3/3/2008 11:39:28 PM
Uh. Memory latency can wreak havoc on performance.
Suppose the difference between AMD and Intel's offerings is just the functional units. Then you'll see performance varies based on the benchmarks that they're executing. But if you crank up the latency, performance drops across the board.
Intel's very visible method of compensating at the moment is to use pretty giant L2 caches. The Penryn-derived Xeon has some pretty gigantic L2 cache sizes. The decrease in cache miss is not linear to the proportional to the cache size increase, but they can't really afford to have a miss. From what I've seen, the Core 2 is a more aggressive superscalar processor, issuing more instructions than Phenom. They really need to keep the memory latency in check to make sure that it can perform. There was this article on Tom's Hardware where they have 3 C2D at the same clock rate, but different cache sizes. Most application benchmarks, when there is variance in performance, the jump from 1MB to 2MB is more significant than 2MB to 4MB.
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