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An document consistent with Intel roadmaps details the company's upcoming 6-core processor

The same slide deck details side-by-side projections of Nehalem with other AMD and Intel processors

George Out estimates the floating point point and integer performance by extrapolating datapoints on the slid  (Source: ZDNet)
Sun confirms what Intel has been dying to tell us, at least off the record

Late last month in Austria, Intel presented Sun with roadmaps discussing details of its upcoming server platforms, including the fairly secret Xeon Dunnington and Nehalem architectures. Unfortunately for some, this presentation ended up on Sun's public web server over the weekend.

Dunnington, Intel's 45nm six-core Xeon processor from the Penryn family, will succeed the Xeon Tigerton processor.  Whereas Tigerton is essentially two 65nm Core 2 Duo processors fused on one package, Dunnington will be Intel's first Core 2 Duo processor with three dual-core banks. 

Dunnington includes 16MB of L3 cache shared by all six processors. Each pair of cores can also access 3MB of local L2 cache.  The end result is a design very similar to the AMD Barcelona quad-core processor; however, each Barcelona core contains 512KB L2 cache, whereas Dunnington cores share L2 cache in pairs.

To sweeten the deal, all Dunnington processors will be pin-compatible with Intel Tigerton processors, and work with the existing Clarksboro chipset.  Intel's slide claims this processor will launch in the second half of 2008 -- a figure consistent with previous roadmaps from the company.

The leaked slide deck also includes more information about Intel's Penryn successor, codenamed NehalemNehalem is everything Penryn is -- 45nm, SSE4, quad-core -- and then some.  For starters, Intel will abandon the front-side bus model in favor of QuickPath Interconnect; a serial bus similar to HyperTransport.

Perhaps the most ambitious aspect of Nehalem? For the first time in 18 years Intel will pair its processors cores up with on-die memory controllers.  AMD made the switch to on-die memory controllers in 2003. For the next three years its processors were almost unmatched by Intel's offerings.  The on-die memory controller can't come a moment too soon. Intel will also roll out tri-channel DDR3 with the Nehalem, and all that extra bandwidth can only be put to use if there are no bottlenecks.

As noted by ZDNet blogger George Ou, the slides contain some rudimentry benchmarks for Nehalem and other publicly available processors.  From this slide deck, Ou estimates Nehalem's SPEC*fp_rate_base2006 at 163 and the SPEC*int_rate_base2006 at 176.  By contrast, Intel's fastest Harpertown Xeon X5482 pulls a measly 80 and 122 SPEC fp and int rate_base2006.

The Nehalem processor more than doubles the floating point performance of its current Penryn-family processors.  Ou adds, "We’ll most likely know by the end of this year what the actual scores are, but I doubt they will be more than 5% to 10% off from these estimated projections."

It's important to note that these estimates are not actual benchmarks.  Intel's document states, "Projections based on *SPECcpu2006 using dual socket Intel Xeon 5160 Processor performance as the baseline." As discussed on DailyTech before, simulated benchmarks offer little substance in favor of the real deal.

As of February 2008, the company plans to launch Nehalem in Q4 2008.

Sun has since removed the slide deck from its website.


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RE: On-die memory controller?
By Gul Westfale on 2/25/2008 8:20:06 AM , Rating: 3
if it's on the motherboard then the cpu has to send a request to the northbridge chip first, andthen wait for teh requested data to arrive. with the memory controller on the same die as the cpu this wait time is eliminated. AMD has been using this on all K8 cpus, and i remember them saying that it cuts latency by 40% compared to a northbridge controller.

also, since the memory traffic passes through a dedicated bus (the on-die controller), the frontside bus is kept free for other things.


RE: On-die memory controller?
By tastyratz on 2/25/08, Rating: 0
RE: On-die memory controller?
By calyth on 3/3/2008 11:39:28 PM , Rating: 2
Uh. Memory latency can wreak havoc on performance.
Suppose the difference between AMD and Intel's offerings is just the functional units. Then you'll see performance varies based on the benchmarks that they're executing. But if you crank up the latency, performance drops across the board.

Intel's very visible method of compensating at the moment is to use pretty giant L2 caches. The Penryn-derived Xeon has some pretty gigantic L2 cache sizes. The decrease in cache miss is not linear to the proportional to the cache size increase, but they can't really afford to have a miss. From what I've seen, the Core 2 is a more aggressive superscalar processor, issuing more instructions than Phenom. They really need to keep the memory latency in check to make sure that it can perform. There was this article on Tom's Hardware where they have 3 C2D at the same clock rate, but different cache sizes. Most application benchmarks, when there is variance in performance, the jump from 1MB to 2MB is more significant than 2MB to 4MB.


RE: On-die memory controller?
By masher2 (blog) on 2/25/2008 10:30:24 AM , Rating: 4
The disadvantage, though, of an on-die memory controller is that it forces you match a cpu to an specific memory technology. Current Intel CPUs can work equally well with DDR2, DDR3, FB-DIMMs...even DDR1, were someone to make a motherboard that supported it. With an on-die controller, new cpus will be specific to one certain type.


RE: On-die memory controller?
By eye smite on 2/25/2008 10:47:50 AM , Rating: 4
Yeah but the FSB has always been a bottleneck for intel and still is. This new controller on the chip will remove that and you'll see even higher numbers in benchmarks and performance as a result. The sacrifice of not being able to use 2 different rams as a result is a small sacrifice IMO. AMD has done well with hypertransport, lets see if intel does as well. I'm sure they will.


RE: On-die memory controller?
By rninneman on 2/25/2008 1:13:14 PM , Rating: 1
The FSB bottleneck is mostly AMD marketing. There is no desktop application that can saturate the FSB on current Intel platforms. The K8 owned the P4 because it was a more efficient core. Only certain specific server workloads benefit from the ODMC. No Intel product yet has an ODMC and they still own everything AMD makes including Barcelona.


RE: On-die memory controller?
By fic2 on 2/25/2008 6:29:25 PM , Rating: 3
Intel made up for the lack of an on-die memory controller by putting HUGE amounts of cache on the chip. With an on-die memory controller they can probably cut this back quite a bit and possibly save die space making the chip size/cost less and lower heat. Of course, this is assuming that the die space used for the on-die memory controller is less than the cache.


RE: On-die memory controller?
By Stratocaster on 2/25/2008 10:49:28 AM , Rating: 2
That's quite interesting^, thanks.


RE: On-die memory controller?
By lagomorpha on 2/25/2008 12:26:24 PM , Rating: 5
That isn't entirely true. One can make an on-die memory controller that has support for more than one type of memory, AMD just didn't with their current generation of CPUs. IIRC aren't later AMD CPUs supposed to have support for multiple memory types?


By phattyboombatty on 2/25/2008 1:34:56 PM , Rating: 3
I believe he was primarily talking about future memory types that are not finalized at the time the CPU is designed and manufactured.

It's not that much of a disadvantage for most people because by the time a new memory type is available, its usually time to upgrade your CPU too.


RE: On-die memory controller?
By Wirmish on 2/26/2008 9:01:09 PM , Rating: 2
The Barcelona/Phenom memory controler is already compatible with the DDR2 and the DDR3, but for now only the DDR2 is used.

Look for "DDR3" in this PDF:
http://tinyurl.com/yv8zmn


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