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Ashwood memory architecture allows for much faster memory speeds

Chipmakers realized long ago that extracting more performance from computer processors could be accomplished in ways other than simply reducing the size of the manufacturing process to squeeze more transistors onto a die.

One of the ways chipmakers improved performance was by building multi-core CPUs, like Intel's Penryn processors, that allow for parallel execution of data. Memory chips haven’t been able to keep up with the performance increases we are seeing in processors making for a bottleneck in the performance of computer systems and other devices.

In order to tackle this problem, a cryptographer named Joseph Ashwood has developed a new memory architecture that allows for multi-core memory.

Ashwood dubbed his memory architecture the Ashwood Architecture. According to EETimes the Ashwood architecture integrates smart controller circuitry next to the memory array on a single chip. This provides parallel access to the memory array for hundreds of concurrent processes leading to increased throughput and lower average access times.

Ashwood says, “My design borrows extensively from today's modern multicore CPUs. As far as concurrency goes, my memory architecture shares some features with Fibre Channel.”

Ashwood says his architecture can hit 16Gbytes per second compared to the DDR2 limit of 12 Gbytes per second. The hallmark of the Ashwood architecture is that the larger the number of bit cells in the memory the better the performance.

Ashwood does admit to a couple downsides to his design. The first is that his design is paper only, though it was independently verified by researchers from Carnegie Mellon University. No design was tested of the architecture at the electrical signal level.

The second drawback is that parallel access overhead of the architecture slows down access time to individual memory cells. However, Ashwood says that the parallel nature of his architecture more than makes up for any slowdowns by executing more commands at the same time.

Ashwood has filed a patent on his architecture that is still pending; until the patent is granted the intricate details of his architecture remain unknown.





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RE: A sign of the times...
By Sulphademus on 1/18/2008 8:50:41 AM , Rating: 2
quote:
One thing I don't understand is that speed of communication between the CPU and memory has not kept up with the speed of the CPU. Honestly though, isn't the biggest bottleneck on modern PCs the HDD?


While not perfect, wasn't the onchip memory controller and hypertransport link of the Athlon 64/Phenom supposed to help here specifically?

As to the hard drive, yeah, they're still ALOT slower than RAM, though I have noticed that Vista does like to preload of an awful lot of stuff into memory. (Seems to target 50% utilization.) So if the OS starts making memory predictions, much like CPUs have done for so long, and pulling this data over to RAM during downtime, this could speed up things some. Or maybe just enough to cover how much heavier and OS Vista is?


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