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Ashwood memory architecture allows for much faster memory speeds

Chipmakers realized long ago that extracting more performance from computer processors could be accomplished in ways other than simply reducing the size of the manufacturing process to squeeze more transistors onto a die.

One of the ways chipmakers improved performance was by building multi-core CPUs, like Intel's Penryn processors, that allow for parallel execution of data. Memory chips haven’t been able to keep up with the performance increases we are seeing in processors making for a bottleneck in the performance of computer systems and other devices.

In order to tackle this problem, a cryptographer named Joseph Ashwood has developed a new memory architecture that allows for multi-core memory.

Ashwood dubbed his memory architecture the Ashwood Architecture. According to EETimes the Ashwood architecture integrates smart controller circuitry next to the memory array on a single chip. This provides parallel access to the memory array for hundreds of concurrent processes leading to increased throughput and lower average access times.

Ashwood says, “My design borrows extensively from today's modern multicore CPUs. As far as concurrency goes, my memory architecture shares some features with Fibre Channel.”

Ashwood says his architecture can hit 16Gbytes per second compared to the DDR2 limit of 12 Gbytes per second. The hallmark of the Ashwood architecture is that the larger the number of bit cells in the memory the better the performance.

Ashwood does admit to a couple downsides to his design. The first is that his design is paper only, though it was independently verified by researchers from Carnegie Mellon University. No design was tested of the architecture at the electrical signal level.

The second drawback is that parallel access overhead of the architecture slows down access time to individual memory cells. However, Ashwood says that the parallel nature of his architecture more than makes up for any slowdowns by executing more commands at the same time.

Ashwood has filed a patent on his architecture that is still pending; until the patent is granted the intricate details of his architecture remain unknown.



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RE: Bandwidth?
By scrapsma54 on 1/17/2008 1:53:07 PM , Rating: 2
Bandwidth is only theoretical. It can only reach its theoretical bandwidth under certain cicumstances, such as A 64 bit Os and a 64-bit processor and pipeline. Every code has to be writen in 64-bits per block. Just like the HD 2900, even though its theoretical band is impressive the blocks are not being processed fast enough for the processor to request more data. Think of boat (memory) and its carrying data to a foreign country (very fast) and reaches its destination, but imagine the next boat has to wait for that boat to finish unloading and load up and leave. Depending on how fast the workers (processors)load and unload and get the boat going, then the next boat can set sail. It seems that Intel has implemented that idea into core. Because of latency, DDR3 is going to have a slow start.


RE: Bandwidth?
By mathew7 on 1/18/2008 7:49:49 AM , Rating: 2
You don't need 64-bit to reach the theoretical bandwidth. The bits are changed at the same speed. The difference is only in overhead, because in 64-bit mode you have not only larger registers, but also more. But you can obtain a bus bottleneck if you do only sums on a large set of data even on 32-bit systems (which can be done using SSE). Of couse, if your processor can process those "bits" fast enough.
And even DDR2 had a slow start after DDR, which also had a slow start after "SD-RAM".
Although "latency" is used in memory relation as the time between command and start of data transfer, the real latency also contains the transfer time (I don't think the CPU cache lets you retrieve bytes before the whole line is fetched). And this is why DDR3 needs higher frequencies to shine: it's higher "start latency" needs to be compensated by burst time.


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