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Ashwood memory architecture allows for much faster memory speeds

Chipmakers realized long ago that extracting more performance from computer processors could be accomplished in ways other than simply reducing the size of the manufacturing process to squeeze more transistors onto a die.

One of the ways chipmakers improved performance was by building multi-core CPUs, like Intel's Penryn processors, that allow for parallel execution of data. Memory chips haven’t been able to keep up with the performance increases we are seeing in processors making for a bottleneck in the performance of computer systems and other devices.

In order to tackle this problem, a cryptographer named Joseph Ashwood has developed a new memory architecture that allows for multi-core memory.

Ashwood dubbed his memory architecture the Ashwood Architecture. According to EETimes the Ashwood architecture integrates smart controller circuitry next to the memory array on a single chip. This provides parallel access to the memory array for hundreds of concurrent processes leading to increased throughput and lower average access times.

Ashwood says, “My design borrows extensively from today's modern multicore CPUs. As far as concurrency goes, my memory architecture shares some features with Fibre Channel.”

Ashwood says his architecture can hit 16Gbytes per second compared to the DDR2 limit of 12 Gbytes per second. The hallmark of the Ashwood architecture is that the larger the number of bit cells in the memory the better the performance.

Ashwood does admit to a couple downsides to his design. The first is that his design is paper only, though it was independently verified by researchers from Carnegie Mellon University. No design was tested of the architecture at the electrical signal level.

The second drawback is that parallel access overhead of the architecture slows down access time to individual memory cells. However, Ashwood says that the parallel nature of his architecture more than makes up for any slowdowns by executing more commands at the same time.

Ashwood has filed a patent on his architecture that is still pending; until the patent is granted the intricate details of his architecture remain unknown.



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RE: Bandwidth?
By blowfish on 1/17/2008 11:38:40 AM , Rating: 0
quote:
I would assume the memory architecture would scale uniformly with the bandwidth of the underlying memory technology. Thus, the architecture implented with DDR3 memory would provide an increase from 25 GB/s to 33 GB/s (using the same percentage increase from the DDR2 memory).

And we all know what "assume" does, don't we?


RE: Bandwidth?
By MAIA on 1/17/2008 12:39:24 PM , Rating: 5
... and don't we always assume before knowing ?


RE: Bandwidth?
By xti on 1/17/2008 2:15:04 PM , Rating: 5
dont you know if you are wrong on the internet, you could die of syphilis?


RE: Bandwidth?
By Obujuwami on 1/17/2008 4:30:17 PM , Rating: 2
AND your children will be born NAKED!!!!

On a more serious note, one thing that a number of people either forget or ignore is that none of this matters if the hard drive bus does not increase with the rest of the technology. I would love to see some SAS type of speeds matched with this RAM. Would be rather nice.


RE: Bandwidth?
By Gentleman on 1/17/2008 6:54:38 PM , Rating: 2
Only if you are wrong about the person being a hot 18 year old and took that mistake home with you....

I wonder how is he able to avoid the issue of clock skewing problems inherent to parallel access lines.


RE: Bandwidth?
By jtemplin on 1/17/2008 1:34:18 PM , Rating: 3
Its called an hypothesis, or an educated guess if you will.


RE: Bandwidth?
By AntDX316 on 1/17/2008 4:30:28 PM , Rating: 2
so its like SATA where SATA can transmit 1 data at a time where Parallel does way more but SATA does it way faster than Parallel does overall


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