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Ashwood memory architecture allows for much faster memory speeds

Chipmakers realized long ago that extracting more performance from computer processors could be accomplished in ways other than simply reducing the size of the manufacturing process to squeeze more transistors onto a die.

One of the ways chipmakers improved performance was by building multi-core CPUs, like Intel's Penryn processors, that allow for parallel execution of data. Memory chips haven’t been able to keep up with the performance increases we are seeing in processors making for a bottleneck in the performance of computer systems and other devices.

In order to tackle this problem, a cryptographer named Joseph Ashwood has developed a new memory architecture that allows for multi-core memory.

Ashwood dubbed his memory architecture the Ashwood Architecture. According to EETimes the Ashwood architecture integrates smart controller circuitry next to the memory array on a single chip. This provides parallel access to the memory array for hundreds of concurrent processes leading to increased throughput and lower average access times.

Ashwood says, “My design borrows extensively from today's modern multicore CPUs. As far as concurrency goes, my memory architecture shares some features with Fibre Channel.”

Ashwood says his architecture can hit 16Gbytes per second compared to the DDR2 limit of 12 Gbytes per second. The hallmark of the Ashwood architecture is that the larger the number of bit cells in the memory the better the performance.

Ashwood does admit to a couple downsides to his design. The first is that his design is paper only, though it was independently verified by researchers from Carnegie Mellon University. No design was tested of the architecture at the electrical signal level.

The second drawback is that parallel access overhead of the architecture slows down access time to individual memory cells. However, Ashwood says that the parallel nature of his architecture more than makes up for any slowdowns by executing more commands at the same time.

Ashwood has filed a patent on his architecture that is still pending; until the patent is granted the intricate details of his architecture remain unknown.



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Drawback?
By phattyboombatty on 1/17/2008 10:20:12 AM , Rating: 1
quote:
Ashwood does admit to a couple downsides to his design. The first is that his design is paper only, though it was independently verified by researchers from Carnegie Mellon University.


The fact that the design is only a concept at the moment is not a "drawback" or "downside" to the design.




RE: Drawback?
By TomZ on 1/17/2008 10:35:05 AM , Rating: 2
Well, going from theory to implementation in real products is not without challenges. For example, will this "new" approach be economically viable relative to alternative implementations?


RE: Drawback?
By phattyboombatty on 1/17/2008 10:42:41 AM , Rating: 3
If the design is determined to be difficult to implement or very expensive to implement, those would be drawbacks. But an idea is not a drawback simply because it is only an idea. When people use the term "drawback" in reference to a particular design, they are generally referring to the negatives encountered once the design is fully implemented or the negatives encountered in actually implementing the design.


RE: Drawback?
By Black69ta on 1/17/2008 5:24:50 PM , Rating: 2
Isn't this similar to the idea behind dual channel memory? Parallel Memory Banks to increase bandwidth? Hasn't Intel already hinted at Quad Channel DDR3 in the enthusiast class Nehalem? Doesn't that accomplish the same thing without increased manufacturing costs?


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