Chipmakers realized long ago that extracting more performance from computer
processors could be accomplished in ways other than simply reducing the size of
the manufacturing process to squeeze more transistors onto a die.
One of the ways chipmakers improved performance was by building multi-core
CPUs, like Intel's
Penryn processors, that allow
for parallel execution of data. Memory chips haven’t been able to keep up with
the performance increases we are seeing in processors making for a bottleneck
in the performance of computer systems and other devices.
In order to tackle this problem, a cryptographer named Joseph Ashwood has
developed a new memory architecture that allows for multi-core memory.
Ashwood dubbed his memory architecture the Ashwood Architecture. According
to EETimes the Ashwood architecture integrates smart controller
circuitry next to the memory array on a single chip. This provides parallel
access to the memory array for hundreds of concurrent processes leading to
increased throughput and lower average access times.
Ashwood says, “My design borrows extensively from today's modern multicore
CPUs. As far as concurrency goes, my memory architecture shares some features
with Fibre Channel.”
Ashwood says his architecture can hit 16Gbytes per second compared to the
DDR2 limit of 12 Gbytes per second. The hallmark of the Ashwood architecture is
that the larger the number of bit cells in the memory the better the
Ashwood does admit to a couple downsides to his design. The first is that
his design is paper only, though it was independently verified by researchers
from Carnegie Mellon University. No design was tested of the architecture at
the electrical signal level.
The second drawback is that parallel access overhead of the architecture
slows down access time to individual memory cells. However, Ashwood says that
the parallel nature of his architecture more than makes up for any slowdowns by
executing more commands at the same time.
Ashwood has filed a patent on his architecture that is still pending; until
the patent is granted the intricate details of his architecture remain unknown.
quote: I would assume the memory architecture would scale uniformly with the bandwidth of the underlying memory technology. Thus, the architecture implented with DDR3 memory would provide an increase from 25 GB/s to 33 GB/s (using the same percentage increase from the DDR2 memory).