Engineers Explain 45nm Delays, Errata
January 16, 2008 10:32 AM
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Engineers blame simulation for quad-core "showstopper"
More than a few people noticed Intel's roadmap originally slated 45nm
desktop quad-core processors for January, only to have the company change the hard launch date to a not-so-firm "Q1 2008." So what happened? In a series of interviews, the tale of quad-core
began to unfold.
Processor engineers, speaking on background, detailed the problem. "Intel is very sensitive to mean time to failures. During a simulation, at high clock frequencies, engineers noticed an increase of potential failures after a designated amount of time."
He continues, "This is not acceptable for desktop customers that require longterm stability. It's a showstopper."
Previous reports of errata degrading the L2 and L3 cache performance were described as "false" -- desktop
processors do not even have L3 cache. Microcode and BIOS updates issued by Intel since November do not fix or address the "showstopper" bug affecting the launch of the
quad-core Q9300, Q9450 and Q9550 processors
The condition does not affect Xeon quad-core processors. Xeon uses a different stepping than the quad-core processors, which fixes this simulated condition. The quad-core 45nm Extreme Edition processor
launched in November
is also unaffected.
The company would not detail when the processors, originally scheduled for a January 20 launch but announced at CES last week, will see the light of day. Conservative estimates from ASUS and Gigabyte put the re-launch sometime in February. Intel completely removed its January 20 launch from its December 2007 roadmap and has not issued a new roadmap since.
Intel spokesman Dan Snyder says more. "We publicly claimed we will launch its 45nm mainstream processors in Q1 2008, and that's exactly what we did." In fact, the company announced 16 new 45nm processors last week; most of which already shipped to manufacturers -- with the exception of the quad-core desktop variants affected by the showstopper simulation bug.
Taiwanese media was
quick to pin the simulated problem on complacency and lack of competition from AMD
. Intel employees quickly denied the allegation, with the additional claim that the report was "humorous."
At CES last week, Snyder elaborates. "The tick-tock model prevents Intel from missing its launch dates. If the 'tock' team misses a target date, it doesn't affect the 'tick' team."
Tick-tock, the strategy of alternating cycles of architecture change and process shrink, became official company policy on January 1, 2006.
As to why the new Macbook Airs still use the 65nm Core 2 Duo processors?
Even after Foxconn alluded the new notebooks would get 45nm treatment
? Another Intel spokesman declined to respond, only stating, "Our partners are free to choose any of Intel's currently supported processors."
Anand Shimpi explores this more
This article is over a month old, voting and posting comments is disabled
RE: I call BS
1/17/2008 2:42:56 AM
First, Intel isn't "on record" anywhere in the article really, it's not an official statement by any means. That, and what is said isn't mutually exclusive with the PC Watch article.
See, engineers do so love the little technicalities. Like that the Xeon is technically a different stepping than the core 2 versions, despite the actual silicon being the same (it's a packaging difference.) And then the technicality that motherboard support for core 2 duo is different than for a core 2 extreme... So on, so forth.
I by no means am trying to say that this isn't a circuits bug. It is. It's not Intel sandbagging. It's not an indication of something gone horribly wrong. It's just more noise than is tolerable on the FSB with 4-layer motherboards. (Dual core has one termination point, quad cores have two termination points, and 4-layer motherboards are inherently more noisy to begin with.)
"I'd be pissed too, but you didn't have to go all Minority Report on his ass!" -- Jon Stewart on police raiding Gizmodo editor Jason Chen's home
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