Engineers Explain 45nm Delays, Errata
January 16, 2008 10:32 AM
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Engineers blame simulation for quad-core "showstopper"
More than a few people noticed Intel's roadmap originally slated 45nm
desktop quad-core processors for January, only to have the company change the hard launch date to a not-so-firm "Q1 2008." So what happened? In a series of interviews, the tale of quad-core
began to unfold.
Processor engineers, speaking on background, detailed the problem. "Intel is very sensitive to mean time to failures. During a simulation, at high clock frequencies, engineers noticed an increase of potential failures after a designated amount of time."
He continues, "This is not acceptable for desktop customers that require longterm stability. It's a showstopper."
Previous reports of errata degrading the L2 and L3 cache performance were described as "false" -- desktop
processors do not even have L3 cache. Microcode and BIOS updates issued by Intel since November do not fix or address the "showstopper" bug affecting the launch of the
quad-core Q9300, Q9450 and Q9550 processors
The condition does not affect Xeon quad-core processors. Xeon uses a different stepping than the quad-core processors, which fixes this simulated condition. The quad-core 45nm Extreme Edition processor
launched in November
is also unaffected.
The company would not detail when the processors, originally scheduled for a January 20 launch but announced at CES last week, will see the light of day. Conservative estimates from ASUS and Gigabyte put the re-launch sometime in February. Intel completely removed its January 20 launch from its December 2007 roadmap and has not issued a new roadmap since.
Intel spokesman Dan Snyder says more. "We publicly claimed we will launch its 45nm mainstream processors in Q1 2008, and that's exactly what we did." In fact, the company announced 16 new 45nm processors last week; most of which already shipped to manufacturers -- with the exception of the quad-core desktop variants affected by the showstopper simulation bug.
Taiwanese media was
quick to pin the simulated problem on complacency and lack of competition from AMD
. Intel employees quickly denied the allegation, with the additional claim that the report was "humorous."
At CES last week, Snyder elaborates. "The tick-tock model prevents Intel from missing its launch dates. If the 'tock' team misses a target date, it doesn't affect the 'tick' team."
Tick-tock, the strategy of alternating cycles of architecture change and process shrink, became official company policy on January 1, 2006.
As to why the new Macbook Airs still use the 65nm Core 2 Duo processors?
Even after Foxconn alluded the new notebooks would get 45nm treatment
? Another Intel spokesman declined to respond, only stating, "Our partners are free to choose any of Intel's currently supported processors."
Anand Shimpi explores this more
This article is over a month old, voting and posting comments is disabled
RE: I call BS
1/16/2008 10:00:19 PM
Back up and consider what you're saying. While the same die, there are indeed potential differences that cause some to be binned for, only capable of lower speeds (or at least at same/similar voltage). Whether these differences also impact longevity of the core if ran under certain parameters may be an issue. It was stated "During a simulation, at high clock frequencies," so why would they need to test these high clock frequencies with a lower binned part anyway?
Maybe they're overvolting them, doing what they know a fair percentage of the enthusiast community will do and finding they don't hold up as well to that as former models did. A lower bin that needs vcore increase to reach speeds moreso than an upper binned part would then be more susceptible to damage merely because they're taking into account what the industry has expected, a certain margin and robustness in the design. It wouldn't look good at all if all the reviewers who got ahold of these had them go up in smoke, typically you see clear thermal issues or instability before something like that happens.
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