Engineers Explain 45nm Delays, Errata
January 16, 2008 10:32 AM
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Engineers blame simulation for quad-core "showstopper"
More than a few people noticed Intel's roadmap originally slated 45nm
desktop quad-core processors for January, only to have the company change the hard launch date to a not-so-firm "Q1 2008." So what happened? In a series of interviews, the tale of quad-core
began to unfold.
Processor engineers, speaking on background, detailed the problem. "Intel is very sensitive to mean time to failures. During a simulation, at high clock frequencies, engineers noticed an increase of potential failures after a designated amount of time."
He continues, "This is not acceptable for desktop customers that require longterm stability. It's a showstopper."
Previous reports of errata degrading the L2 and L3 cache performance were described as "false" -- desktop
processors do not even have L3 cache. Microcode and BIOS updates issued by Intel since November do not fix or address the "showstopper" bug affecting the launch of the
quad-core Q9300, Q9450 and Q9550 processors
The condition does not affect Xeon quad-core processors. Xeon uses a different stepping than the quad-core processors, which fixes this simulated condition. The quad-core 45nm Extreme Edition processor
launched in November
is also unaffected.
The company would not detail when the processors, originally scheduled for a January 20 launch but announced at CES last week, will see the light of day. Conservative estimates from ASUS and Gigabyte put the re-launch sometime in February. Intel completely removed its January 20 launch from its December 2007 roadmap and has not issued a new roadmap since.
Intel spokesman Dan Snyder says more. "We publicly claimed we will launch its 45nm mainstream processors in Q1 2008, and that's exactly what we did." In fact, the company announced 16 new 45nm processors last week; most of which already shipped to manufacturers -- with the exception of the quad-core desktop variants affected by the showstopper simulation bug.
Taiwanese media was
quick to pin the simulated problem on complacency and lack of competition from AMD
. Intel employees quickly denied the allegation, with the additional claim that the report was "humorous."
At CES last week, Snyder elaborates. "The tick-tock model prevents Intel from missing its launch dates. If the 'tock' team misses a target date, it doesn't affect the 'tick' team."
Tick-tock, the strategy of alternating cycles of architecture change and process shrink, became official company policy on January 1, 2006.
As to why the new Macbook Airs still use the 65nm Core 2 Duo processors?
Even after Foxconn alluded the new notebooks would get 45nm treatment
? Another Intel spokesman declined to respond, only stating, "Our partners are free to choose any of Intel's currently supported processors."
Anand Shimpi explores this more
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RE: I call BS
1/16/2008 1:44:14 PM
What makes you think Intel is running these simulations right now, as opposed to months ago? Or that Intel even stops running simulations on its processors? Last I heard the Intel simulation cluster was about 5,000 servers -- they might as well be doing something?
Well, you can believe this signal integrity thing all you want. Intel denies it, a few random blogs speculate it, and this article pins it on another problem.
In the end, it pretty much doesn't matter which makes me wonder why Intel would lie about it? And not just clever wording -- this would be a bold faced lie.
My personal opinion? The EE is probably affected too. I didn't see Intel state anything about it in the article, and that was just Kris's speculation added in at the end.
RE: I call BS
1/17/2008 2:59:59 AM
Well first, maybe 5,000 servers at one site =P Second, those are primarily for simulation of the design well before you actually have silicon to play around with. (That and processing the design for tapeout...) As you can probably guess from those statements, those servers are kept plentifully busy playing around with what's coming up next.
Sure, technically all the 45nm quad core processors would be affected by the issue. It's not something peculiar to the mainstream desktop ones, it's just that's the only place where it ends up happening when run at spec because the spec includes cheaper mainstream motherboards. It's a simple fact of high speed transmission lines that both the quality of the line -and- the termination play a role in signal integrity. The better quality of the line on 6 layer motherboards simply makes up for the slight slip on termination on the quad cores.
All of the above is speculation based upon playing around a tad with the other end of the link. The only people at Intel that really know what the issue would be is likely one silicon validation team, the corresponding IO/design team, and management going up. As the frequent posting of things from Circuit to The Inquirer goes to show, giving employees information that they needn't know just tends to get it leaked. Kinda humorous to hear more about project status from the various computer websites than from any internal information =P
"There is a single light of science, and to brighten it anywhere is to brighten it everywhere." -- Isaac Asimov
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