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Engineers blame simulation for quad-core "showstopper"

More than a few people noticed Intel's roadmap originally slated 45nm Penryn desktop quad-core processors for January, only to have the company change the hard launch date to a not-so-firm "Q1 2008." So what happened?  In a series of interviews, the tale of quad-core Penryn began to unfold. 

Processor engineers, speaking on background, detailed the problem. "Intel is very sensitive to mean time to failures.  During a simulation, at high clock frequencies, engineers noticed an increase of potential failures after a designated amount of time."

He continues, "This is not acceptable for desktop customers that require longterm stability. It's a showstopper."

Previous reports of errata degrading the L2 and L3 cache performance were described as "false" -- desktop Penryn processors do not even have L3 cache. Microcode and BIOS updates issued by Intel since November do not fix or address the "showstopper" bug affecting the launch of the quad-core Q9300, Q9450 and Q9550 processors

The condition does not affect Xeon quad-core processors.  Xeon uses a different stepping than the quad-core processors, which fixes this simulated condition.  The quad-core 45nm Extreme Edition processor launched in November is also unaffected.

The company would not detail when the processors, originally scheduled for a January 20 launch but announced at CES last week, will see the light of day. Conservative estimates from ASUS and Gigabyte put the re-launch sometime in February.  Intel completely removed its January 20 launch from its December 2007 roadmap and has not issued a new roadmap since. 

Intel spokesman Dan Snyder says more. "We publicly claimed we will launch its 45nm mainstream processors in Q1 2008, and that's exactly what we did."  In fact, the company announced 16 new 45nm processors last week; most of which already shipped to manufacturers -- with the exception of the quad-core desktop variants affected by the showstopper simulation bug.

Taiwanese media was quick to pin the simulated problem on complacency and lack of competition from AMD.  Intel employees quickly denied the allegation, with the additional claim that the report was "humorous." 

At CES last week, Snyder elaborates.  "The tick-tock model prevents Intel from missing its launch dates.  If the 'tock' team misses a target date, it doesn't affect the 'tick' team."

Tick-tock, the strategy of alternating cycles of architecture change and process shrink, became official company policy on  January 1, 2006. 

As to why the new Macbook Airs still use the 65nm Core 2 Duo processors? Even after Foxconn alluded the new notebooks would get 45nm treatment?  Another Intel spokesman declined to respond, only stating, "Our partners are free to choose any of Intel's currently supported processors."  Anand Shimpi explores this more.


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RE: I call BS
By Khato on 1/16/2008 12:05:05 PM , Rating: 3
Eh, I prefer the explanation from PC watch a week or so ago - there are stability problems for 45 nm quad core processors on 4 layer motherboards. Specifically, that the FSB gets a tad bit too noisy (quads have to share the FSB between two die after all.)

It lines up purrfectly with this article no less - just without the silly notion that the EE has lesser MTTF parameters than the mainstream. The EE simply has stricter motherboard requirements as far as Intel's concerned, which makes this issue disappear.

Do note that this is an actual issue, either with the IO buffers or something with packaging. But it's only an issue because it's a good idea to make certain these mainstream processors will run in the cheapo motherboards that some are likely to put them in. (aka, OEM's would really complain if they had to step up to 6 layer motherboards.)


RE: I call BS
By James Holden on 1/16/2008 12:52:08 PM , Rating: 2
Even with Intel on record you prefer PC Watch's explanation?

Maybe PC Watch is right. But it seems pretty cut and dry when the whole company goes on record.

As for EE, did anyone stop and consider that maybe EE was a different stepping than the desktop chips? After all, its practically a Xeon anyway, and the Xeons aren't affected.


RE: I call BS
By TomZ on 1/16/2008 12:59:21 PM , Rating: 2
The problem is that Intel's so-called "explanation" doesn't really make any sense, as has been pointed out by a few other posters here.

Like, for example, why is Intel still running simulations against a processor which was supposed to release on the 20th? And a processor whose EE variant released a couple of months ago?

No, I think it makes more sense that there may be signal integrity problems on motherboards, and that the simulations are on the motherboards and not the processor itself. Just my guess with the limited information at this point.


RE: I call BS
By James Holden on 1/16/2008 1:44:14 PM , Rating: 2
What makes you think Intel is running these simulations right now, as opposed to months ago? Or that Intel even stops running simulations on its processors? Last I heard the Intel simulation cluster was about 5,000 servers -- they might as well be doing something?

Well, you can believe this signal integrity thing all you want. Intel denies it, a few random blogs speculate it, and this article pins it on another problem.

In the end, it pretty much doesn't matter which makes me wonder why Intel would lie about it? And not just clever wording -- this would be a bold faced lie.

My personal opinion? The EE is probably affected too. I didn't see Intel state anything about it in the article, and that was just Kris's speculation added in at the end.


RE: I call BS
By Khato on 1/17/2008 2:59:59 AM , Rating: 2
Well first, maybe 5,000 servers at one site =P Second, those are primarily for simulation of the design well before you actually have silicon to play around with. (That and processing the design for tapeout...) As you can probably guess from those statements, those servers are kept plentifully busy playing around with what's coming up next.

Sure, technically all the 45nm quad core processors would be affected by the issue. It's not something peculiar to the mainstream desktop ones, it's just that's the only place where it ends up happening when run at spec because the spec includes cheaper mainstream motherboards. It's a simple fact of high speed transmission lines that both the quality of the line -and- the termination play a role in signal integrity. The better quality of the line on 6 layer motherboards simply makes up for the slight slip on termination on the quad cores.

All of the above is speculation based upon playing around a tad with the other end of the link. The only people at Intel that really know what the issue would be is likely one silicon validation team, the corresponding IO/design team, and management going up. As the frequent posting of things from Circuit to The Inquirer goes to show, giving employees information that they needn't know just tends to get it leaked. Kinda humorous to hear more about project status from the various computer websites than from any internal information =P


RE: I call BS
By mindless1 on 1/16/2008 9:48:56 PM , Rating: 2
It's quite simple, a simulation of long-term effects would seek as much as possible to be ran over a long term. The idea that one can just make it run hot, or overvolt, isn't the same as just keeping it running and seeing what happens (possibly with either or both of the former also preconditions).

It does not seem likely to be a motherboard signal integrity problem at all.The EE would then be effected and rather than lose face about a, err, flaw, they'd issue a warning about updated motherboard guidelines.


RE: I call BS
By Khato on 1/17/2008 2:42:56 AM , Rating: 3
First, Intel isn't "on record" anywhere in the article really, it's not an official statement by any means. That, and what is said isn't mutually exclusive with the PC Watch article.

See, engineers do so love the little technicalities. Like that the Xeon is technically a different stepping than the core 2 versions, despite the actual silicon being the same (it's a packaging difference.) And then the technicality that motherboard support for core 2 duo is different than for a core 2 extreme... So on, so forth.

I by no means am trying to say that this isn't a circuits bug. It is. It's not Intel sandbagging. It's not an indication of something gone horribly wrong. It's just more noise than is tolerable on the FSB with 4-layer motherboards. (Dual core has one termination point, quad cores have two termination points, and 4-layer motherboards are inherently more noisy to begin with.)


RE: I call BS
By lindejos on 1/21/2008 1:09:49 PM , Rating: 3
Wait a minute, who went on record? According to the article some faceless process engineer, who allegedly works at Intel? Don't you think that if Intel was going to "go on record" there would be a press release?

The only thing that the company actually said on record is "We publicly claimed we will launch our 45nm mainstream processors in Q1 2008, and that's exactly what we did." That was said by Dan Snyder who is a company spokesman. Here's a link to an actual sourced quote: http://www.techreport.com/discussions.x/13756.

"On Record" has to be sourced to an actual person you can prove works for the company. Let's call this MTBF or Errata issue "speculation."


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