backtop


Print 17 comment(s) - last by Tim Thorpe.. on May 4 at 5:12 PM

Taiwanese Manufactures receive updated AMD roadmap indicating quad core processors

Chinese hardware site HKEPC (english) is reporting that hardware firms in Taiwan have received updated roadmaps from AMD showing quad core Opteron and x64 -- with shipments starting in the second half of ’07 and continuing on in to ‘08.

The website claims the first quad core AMD part will be an Opteron code named Deerhound and will feature a shared L2 cache 2 channel RDDR2 Socket F, will be produced using AMD’s 65nm process, and will debut the second half of ’07. Showing up during the first half of ’08 will be Greyhound -- AMD’s quad core desktop part with a shared L2 cache and DDR2/3 with HyperTransport 3.0 support.

Rounding out AMD’s roadmap for the next 2 years is Zamora; an Opteron with a shared L3 cache and FB-DIMM support and HyperTransport 3.0. Last, the website claims we will see Cadiz aimed at the workstation market which has a shared L2 cache and supports DDR2/3 and HyperTransport 3.0.





Comments     Threshold


This article is over a month old, voting and posting comments is disabled

By Sahrin on 5/4/2006 10:06:17 AM , Rating: 2
The stupidity of that comment is exceeded only by its childishness. No one said AMD invented everything, just that currently, Intel is playing "catch-up" since AMD released the K8 (really since they released the K7, but that's another matter).

As far as HT being the "Cat's meow", I too was led to believe this, perhaps there is an additional explanation (not 4 memory channels per core, not wanting to put control logic for 4x1 or 4x2 MB of hyperfast L2 SRAM on die with 4-8 HT links, MCH et al. Perhaps its just that AMD feels that the significant speed boost from HT2 to HT3 will negate any performance decrease caused by cache overwrites/inconsistencies? I really the the shared L2 is just an attempt to spare AMD some logic, especially considering these chips are likely larger at 65nm than dual core hammer is at 90nm.



By DallasTexas on 5/4/2006 12:26:22 PM , Rating: 2
Yep, that was stupid and childish but I was looking to appeal to the readers in the forum for a corresponding response. I need some friends in here. Will you be my friend?

Back to the topic..
"...perhaps there is an additional explanation (not 4 memory channels per core, not wanting to put control logic .."

Nah, I think Intel had a better approach with shared/multi-ported cache and AMD is following. I still think "HyperTransport" sounds cool even though it's not that great for cache coherency but should continue to sell well. I mean, "Hyper" sounds cool and "Shared" sounds, well, it's "not mine". Again, Hyper will sell to this forum for a while. :-)


By MrKaz on 5/4/2006 10:19:24 AM , Rating: 2
Shared cache is not an invention, besides that doesn’t also mean that it’s better. I bet there are some times where dedicated core cache is better than a shared one....


By BaronMatrix on 5/4/2006 12:39:17 PM , Rating: 2
HT is a bus. it has nothing to do with cache coherency. Coherency is a chipset function. L3 will give them better coherency because it provides an independent buffer for large scale systems. That is why AMD is not scaling that well above 8way, except for the Horus from Newisys which uses a special chipset. That's why Xeons use large L3.


By DallasTexas on 5/4/2006 1:44:34 PM , Rating: 2
"..HT is a bus. it has nothing to do with cache coherency. Coherency is a chipset function.."

OK; No and No. You struck out but the first was a foul ball.

AMD uses HyperTransport with a proprietary cache coherency extension of HyperTransport as part of their Direct Connect Architecture - for you guessed it, cache coherency.
I'll have to find a chipset that does cache coherency for multiprocessors so I'll reserve judgement. However, I'll give you a big fat no on that one for now.


By Viditor on 5/4/2006 2:02:11 PM , Rating: 2
quote:
AMD uses HyperTransport with a proprietary cache coherency extension of HyperTransport as part of their Direct Connect Architecture

Cache coherency is maintained in 2 ways with AMD...

1. Through cHT links (Coherent HT links) which are from chip to chip directly
2. Through the internal cross bar switch on dual cores. This is between the 2 seperate caches of a dual core CPU.

Intel uses a FSB (which AMD does not), so cache coherency is routed through the FSB (Northbridge).


By Viditor on 5/4/2006 2:02:12 PM , Rating: 2
quote:
AMD uses HyperTransport with a proprietary cache coherency extension of HyperTransport as part of their Direct Connect Architecture

Cache coherency is maintained in 2 ways with AMD...

1. Through cHT links (Coherent HT links) which are from chip to chip directly
2. Through the internal cross bar switch on dual cores. This is between the 2 seperate caches of a dual core CPU.

Intel uses a FSB (which AMD does not), so cache coherency is routed through the FSB (Northbridge).


Don't beleive it.
By Phynaz on 5/4/2006 9:50:09 AM , Rating: 1
AMD roadmaps as a rule don't have spelling and formatting errors in them.




RE: Don't beleive it.
By Viditor on 5/4/2006 10:41:45 AM , Rating: 2
I'm not buying it either...
AMD has been quite consistent in their comments that:
1. 65nm production begins by Sept for release by Q1
2. First release will be their Socket F servers including quad core CPUs by Q1.

It should also be noted that:

1. The "roadmap" does not use AMD's coluor shceme
2. There's no AMD logo to be seen...


RE: Don't beleive it.
By KristopherKubicki (blog) on 5/4/2006 10:46:38 AM , Rating: 2
Hi,

The graphic in this article is DailyTech's. The graphic in the source article is HKEPC's standard for roadmap reproduction. DailyTech and HKEPC rarely publish images directly from the roadmap because of watermarks.

Kristopher


RE: Don't beleive it.
By Viditor on 5/4/2006 10:51:44 AM , Rating: 2
Thanks for the clarification Kristopher!
If I may ask your opinion, do YOU believe the roadmap is genuine?


RE: Don't beleive it.
By Tim Thorpe on 5/4/2006 5:12:07 PM , Rating: 2
I may be able the answer that for you note I'm not speaking for Kristopher on this but from my own personal experiences. As you're probably well aware AMD is in no big hurry to let the competition know of it's future plans. I will say it is consistent with what I've seen from Intel’s 10 year projections (re: http://www.intel.com/technology/architecture/platf... ) and I am assuming for the sake of conversation that AMD will follow a similar path if not from direct competition then purely out of evolution of the technologies. Do note that this is 3rd party news so take it with a grain/spoonful/pound of salt. I hope that answers your question.

Tim


RE: Don't beleive it.
By Furen on 5/4/2006 12:41:07 PM , Rating: 2
Just so you know this roadmap does not include Brisbane and its equivalents (1st gen 65nm parts). These are, in fact, second/third generation 65nm parts but it is the first time AMD actually mentions quad-core on its roadmap, hence its news-worthiness.

Now, if you want to believe rumors... TheInq has mentioned that rev F has 4 SRI ports (for CPU cores, in case AMD needs to accelerate quad-core) so quad could be done on it, they've also mentioned that rev G (Brisbane, et al.) is planned to be AMD's initial quad core part.


What process are they using?
By hstewarth on 5/4/2006 10:15:02 AM , Rating: 2
I am curious what process are AMD using, If its what they currenty using they likely going to have heat issues.




By Viditor on 5/4/2006 10:43:50 AM , Rating: 2
quote:
I am curious what process are AMD using

What do you mean by "process"?
They will be at 65nm and using the improved SiGe straining...this was announced months ago.


"So if you want to save the planet, feel free to drive your Hummer. Just avoid the drive thru line at McDonalds." -- Michael Asher
Related Articles
AMD's Next-gen Socket F Revealed
February 23, 2006, 5:02 PM













botimage
Copyright 2015 DailyTech LLC. - RSS Feed | Advertise | About Us | Ethics | FAQ | Terms, Conditions & Privacy Information | Kristopher Kubicki