Toshiba presented in the VLSI symposium on Tuesday a new
three dimensional memory cell array structure that enhances cell density and
data capacity with minimal increase in the chip die size, but without the need
to rely on advances in process technology.Existing memory stacking technologies simply stack
two-dimensional memory array on top of another, repeating the same set of
processes. While this achieves increased memory cell density, it makes the
manufacturing process longer and more complex.
Toshiba’s new approach to etching technology drives a
through-hole down through a stacked substrate, creating a multi-layer sandwich
of gate electrodes and insulator films. Pillars of silicon lightly doped with
impurities are deposited to fill in the holes. The gate electrode wraps around
the silicon pillar at even intervals, and a pre-formed nitride film for
data-retention, set in each joint, function as a NAND cell.
Samsung previously announced 3D stacking technologies for NAND memory, though a quick glance at each layout demonstrates the apparent complexity of the Toshiba approach. Hynix, IBM and Hynix have also revealed cell-stacking technologies of one form or another.
Toshiba’s new array increases density without increasing
chip dimension, as the number of connected elements increases in direct
proportion to stack height. For example, a 32-layer stack realizes 10 times the
integration of a standard chip formed with the same generation of technology. The
innovative design is a potential candidate technology for meeting future demand
for higher density NAND flash memory.
The company would not state exactly how much it can improve memory density with this approach, though the corporate press release states a 32-layer stack could realize a 10-fold increase in cell density without increasing the chip dimension.
