A diagram of the Itanium 2 "Montecito" die released at Fall IDF 2005
Intel's newest Itanium has some dramatic changes, but enough to stay competitive?

For my twenty-third birthday tomorrow, July 18, 2006, Intel is set to announce its newest addition to the Itanium 2 in three years.  Montecito marks a lot of first for the Itanium line.  For example, Montecito is:
  • Intel's first Itanium on the 90nm process
  • Intel's first dual-core Itanium
  • Intel's first Itanium with Virtualization Technology (VT) and Cache Safe Technology (CST)
  • Intel's first Itanium to feature processor numbers
The transition for Itanium 2 from 130nm to 90nm alone is a major step for the company.  The 130nm process size was already long in the tooth in 2003 when Itanium 2 Fanwood and Madison made an appearance.  Although the rest of Intel's processor manufacturing has for the most part switched to 65nm, Itanium 2 is just starting 90nm with Montecito.

Of course, a die shrink was inevitable to cram those 1.7 billion transistors on Montecito.  The high end model, Itanium 2 9050, utilizes a 24MB L3 cache which is split between the two processor cores on-chip

According to Intel documentation, existing Madison systems can use Montecito as a drop in replacement.  The 400 MHz FSB E8870 chipset, announced in August of 2000, still powers the Itanium line.  Interestingly enough, while some Madison processors were rated to 667 MHz FSB, the new Montecito chips top out at 533 MHz FSB, with a clock frequency that tops out around 1.6 GHz.  Since Intel has moved the entire product line to a number-based naming system, below is a table of the newest Intel chips.

Intel Itanium 2 "Montecito" Processors
9050 2 x 1.6 GHz 533 MHz 24MB 104W
9040 2 x 1.6 GHz 533 MHz 18MB 104W
9030 2 x 1.6 GHz 533 MHz 8MB 104W
9020 2 x 1.42 GHz 533 MHz 12MB 104W
9015 2 x 1.4 GHz 400 MHz 12MB 104W
9010 1.6 GHz 533 MHz 6MB 75W

The Itanium 2 9010 will be Intel's only single-core Montecito at launch.  Unlike Intel's Tulsa (scheduled to launch August 27, 2006) Xeon processor, Montecito will not feature shared L3 cache.  This has been a planned feature for Montecito almost as long as there has been a codename for it. 

Like previous Itaniums, Montecito features Hyper-Threading on most of its lineup.  Thus, dual-core processors will actually appear as logical quad-core processors.  The only chips not getting Hyper-Threading with this iteration are the dual-core Montecito 9030 and the single-core Montecito 9010.

Intel made the claim a year ago that Montecito is more than 60% faster than the Madison core, claiming a four-socket (8-core) system was able to achieve a LINPACK score of 45 GFLOPs.  To put that in perspective, a four-socket HP ProLiant BL45p loaded with Opteron 880s (4 processors, 2-cores per processor) has a LINPACK score of around 16 GFLOPs (PDF). Considering the $10B USD cash influx the Itanium line just received, we would expect Montecito to live up to the hype.

Montecito is expected to be replaced by Montvale and Tukwila CPUs, but Intel has not released a for these chips yet.

“Then they pop up and say ‘Hello, surprise! Give us your money or we will shut you down!' Screw them. Seriously, screw them. You can quote me on that.” -- Newegg Chief Legal Officer Lee Cheng referencing patent trolls
Related Articles
16MB of L3 Cache: Intel's "Tulsa"
May 28, 2006, 7:12 PM

Latest Headlines

Latest Blog Posts
T-Mobile Data Problems
Saimin Nidarson - Oct 20, 2016, 10:17 AM

Copyright 2016 DailyTech LLC. - RSS Feed | Advertise | About Us | Ethics | FAQ | Terms, Conditions & Privacy Information | Kristopher Kubicki