Section diagram of conventional MCP and new 16-Chip
These chips are made with frickin' laser beams
Samsung Electronics announced that it has developed the industry’s first process to enable production of a 16-chip multi-chip package (MCP) of memory. Samsung’s new 16-chip MCP technology, when applied to 8Gb NAND flash chips, can enable up to a 16GB MCP solution.
Advanced multi-chip package technology requires a combination of key processes such as wafer thinning, redistribution layer, chip sawing and wire bonding.
To increase the number of chips stacked vertically, Samsung introduced wafer-thinning technology that eliminates 24/25th of the thickness of each fabricated wafer to reduce the overall thickness to only 30-microns. This is just 65 percent the thickness of the 45-micron 10-chip MCP wafer Samsung developed in 2005 and similar to the size a human cell, which measures 20 to 30 microns.
As part of its MCP development, Samsung also developed a new laser-cutting technology to cut the wafer into individual chips. This new cutting process prevents the memory chips from breaking into pieces when they are cut using conventional blade sawing technology, which was originally designed only for sawing wafers up to 80 microns thick.
To vertically stack identically-sized dies, a redistribution layer technology also is applied in Samsung’s new multi-stack MCP process, to enable wafer fabricators to adhere the wire contacts from just one side, unlike the conventional method of extending wire connection from both sides of each chip. Along with a single wire contact per die, the dies are placed in a zigzag stack to minimize the use of space and the length of the wire connectors. Moreover, the thickness of the adhesive has been reduced to 20 microns bringing the height of a 16-die stack to 1.4mm. For comparison, Samsung's 10-chip MCP uses a 60-micron adhesive layer and has a total height of 1.6mm.
This isn't the first time Samsung has experimented with stacking. Samsung announced in April its 3D memory packaging technology which used "through silicon" interconnects.
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