Samsung Electronics has released details on its own all-DRAM
stacked memory package using through-silicon via (TSV) technology. The new
wafer-level-processed stacked package (WSP) consists of four 512Mb DDR2 DRAM chips
that offer a combined 2Gb of high density memory. Using the TSV-processed 2Gb
DRAMs, Samsung says it can create a 4GB DIMM based on advanced WSP technology,
while reducing overall package size, power use and increasing chip speed.
In today’s MCPs, memory chips are connected by wire bonding,
requiring vertical spacing between dies that is tens of microns deep. That wire
bonding process also requires horizontal spacing on the package board hundreds
of microns wide for the die-connecting wires. Samsung’s WSP technology forms
laser-cut micron-sized holes that penetrate the silicon vertically to connect
the memory circuits directly with a copper filling, eliminating the need for
gaps of extra space and wires protruding beyond the sides of the dies. These
advantages permit a significantly smaller footprint and thinner package.
Inside the new WSP, the TSV is housed within an aluminum pad
to escape the performance-slow-down effect caused by the redistribution layer. Samsung
announced a similar method last year involving NAND flash
dies, but the company says that, due to the complexity of DRAM stacking,
this represented a much more difficult engineering feat than that accomplished
with the first WSP.
In addition, as the back side of the wafer is ground away to
make a thinner stack of multiple dies, the wafer has had a tendency to curve,
creating physical distortion in the die. To overcome this additional critical
concern in designing low-profile, high-density MCPs containing DRAM circuitry,
Samsung’s proprietary wafer-thinning technology, announced last year,
has been applied to improve the thin-die-cutting process.
“The innovative TSV-based MCP (multi-chip package) stacking
technology offers next-generation packaging solution that will accommodate the
ever-growing demand for smaller-sized, high-speed, high-density memory,” said
Tae-Gyeong Chung, vice president, Interconnect Technology Development Team,
Memory Division, Samsung Electronics. “In addition, the performance
advancements achieved by our WSP technology can be utilized in many diverse
combinations of semiconductor packaging, such as system-in-package solutions
that combine logic with memory.”
The latest developments in chip stacking and through through-silicon
via are heralding announcements from chip companies saying that Moore’s Law
will continue to ring true, especially in light of the considerable concern that MCP would soon suffer
from performance limitations when connected using current technologies.
Earlier this month, IBM announced it own
chip-making breakthrough using through-silicon via technology, boasting
that the technique shortens wire lengths inside chips up to 1000 times and
allows for the addition of up to 100 times more channels, or pathways, for that
information to flow compared to traditional chips.
IBM says that it is already running chips using the
through-silicon via technology in its manufacturing line and will begin making
sample chips using this method available to customers in the second half of
2007, with production in 2008. Samsung, on the other hand, says that its
new and more complex DRAM stacked package design will support next-generation
computing systems beginning in 2010.