Last month I attended the International Solid-State Circuit Conference San Francisco.  ISSCC, as it's commonly known, is the platform major tech companies use to unveil the inner-workings of its next-generation processors.

This year IBM announced its upcoming eDRAM strategy and Intel announced more details on the Teraflops Research Chip.  Several other key platforms were buried in the announcements, especially from the smaller companies.  Since the visual supplement just came out this week, I've revisited some of the less known topics from ISSCC.

I've split up my coverage with regard to the conference in several pieces; the first part covers presentations from several companies, including PA Semi’s low power design, Intel’s Merom processor and Sun’s Niagara II system on a chip.  I also discusses technology NEC has developed to predict failures in integrated circuits, which can be used with redundancy to avoid interruptions.

My follow-up coverage will include details from AMD, Intel and IBM.