Clearing up a little confusion

Several weeks ago, I wrote an article about the K8L architecture during AMD's analyst day.  In the article, I stated the following:

Additionally, Hester revealed some more information about the cache specifics on K8L.  Each K8L core will have 64KB of dedicated L1 cache, followed by 512KB of dedicated L2 cache.  The base models of K8L will have 2MB of shared L3 cache, but Hester also went on to claim that adding more L3 cache was in the company’s roadmap.  One thing AMD representatives have not particularly touched on is the cache reduction from 64+64KB (data+instruction) to 32+32KB.  AMD employees have assured us this move is logical with the addition of L3 cache. 

This is not correct, and I had unfortunately misinterpreted slides from AMD, and there was some confusion with details that were released to the public as well.  AMD representatives have contacted me claiming "Haven't got a definitive answer yet, but I'd be very surprised if anyone has changed the L1 cache sizes which has been 64KB data + 64KB instruction since we first introduced K7 way back in the old days."  The L2 and L3 cache details are still the same. I apologize for any confusion this may have caused.

Secondly, I would like to address the AMD Optimization Utility article we posted on a few days ago.  In this article, we claimed:

The AMD Dual-Core Optimizer utility could possibly be the rumored "Reverse Hyper-Threading" patch that would improve single thread application and games performance by having dual-core processors show up as a single core processor in applications. AMD has declined to comment on "Reverse Hyper-Threading."

Just to emphasize this, DailyTech does not believe the utility is the precursor to RHT -- in fact we've not seen any shred of evidence that would suggest RHT even exists.  My best guess is that someone saw the utility before AMD officially announced it, and several bad translations later it morphed into RHT, hence the rumors.

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