Hardware
PCIe 2.0 Ratified
Gabriel Ikram (Blog) - January 16, 2007 5:54 AM
Hail, new PCIe motherboards of twice the bandwidth!
This article was first published on HWUpgrade.com.
Yesterday the PCI Express Special Interest Group, also known as PCI-SIG, announced that it finalized the PCI Express 2.0 specifications. The specifications initially entered the release candidate stage a little over three months ago.
The new PCI Express 2.0 Bus Specification doubles the interconnect bit rate from 2.5 GT/s to 5 GT/s. PCI-SIG describes this bandwidth hike as “by far the most important feature of the PCI Express 2.0 specifications.” Like ethernet, 20% of all signalling on PCIe is dedicated to overhead. Thus for every 10 bits transfered, 8 bits (or 1 byte) are actual data. Thus, doubling the interconnect bit rate increases the aggregate bandwidth of a single PCI Express x16 slot to 16 GBps.
When asked about the cost effectiveness of PCIe 2.0, a PCI-SIG representative claimed "A PCI Express 1.1 x8 link (8 lanes) yields a total aggregate bandwidth of 4GBytes/s, which is the same bandwidth obtained from a PCI Express 2.0 x4 link (4 lanes) that adopts the 5GT/s signaling technology. This can result in significant savings in platform implementation cost while achieving the same performance level. Backward compatibility is retained as existing 2.5 GT/S adapters can plug into 5.0 GT/S slots and will run at the slower rate. Conversely, new PCIe 2.0 adapters running at 5.0 GT/S can plug into existing PCIe slots and run at the slower rate of 2.5 GT/S." Both 2.5GT/s and 5GT/s signaling are retained in the 2.0 specification.
In addition to the bandwidth increase, the new specifications have a number of other improvements. Dynamic link speed management has been added allowing software to control the frequency at which Express 2.0 links operate. Under the new specification, software is also notified of changes in link frequency and width. The Express 2.0 interface also implements a new feature that gives software optional controls to manage packet routing on the interconnect. The power limit can now also be redefined in order to accommodate devices that consume higher power.
PCI-SIG outlines the new features as:
- Enhanced Completion Timeout Control, which includes required and optional aspects, reduces false timeouts and increases the ability to ‘tune’ the timeouts.
- Function Level Reset and Access Control Services, giving enhanced robustness and support of certain IOV features -- though this feature is labeled as optional/
- Slot Power Limit Changes to allow for higher powered slots, which support the newer, high-performance graphics cards. This new feature works in tandem with the 300W Card Electro-mechanical specification.
- Speed Signaling Controls to enable software to determine whether a device can operate at a specific signaling rate, which can be used to reduce power consumption, as well as provide gross level I/O to memory.
The new interface will prove to be particularly useful for video cards whose performance is limited as a result of lower I/O throughput. Manufacturers will be able to use the faster channels for shared memory graphics which uses system memory to boost performance.
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