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MIT's new nanoruler lithography machine. A 300mm silicon waits to be etched by the scanning-beam interference lithography system.  (Source: Ralf Heilmann, Massachusetts Institute of Technology)
They scaled down, down, down and the transistors went higher.

Lithography is the backbone of every computer chip manufacturer on the planet. Etching tiny lines into silicon wafers to create working circuits brings us our high speed computers and electronic devices. Presently, the industry is floating around the 45nm to 65nm detail mark with 32nm looming closely on the horizon.

What does this mean? The closer together these circuits can be cut, the more features, in most cases transistors, that can be packed onto the same surface area of a single chip. Modern processors are cramming two, four, and even eight processing cores into the space of what a single core consumed just a few years ago.

Part of the growing concern of the semiconductor industry is that further shrinking the lithography process is becoming quite difficult. DailyTech reported on various technologies that promise to take integrated circuits to the next level, but thus far none are being utilized for various reasons.

Engineers at the Massachusetts Institute of Technology have come up with a technique that could advance standard lithography processes, rather than reinventing them. Known as scanning-beam interference lithography, the process currently allows them create 25nm features separated by 25nm gaps – less than half the size of the current 65nm process. Not only can SBIL create smaller features, it can do so over a larger area than typical interference lithography, producing more cut surface more quickly.

The entire process was built from the ground up by MIT graduate students and members of the MIT Kavli Institute of Astrophysics and Space Research. Graduate student Yong Zhao developed a new image reversal process while Chih-Hao Chang, another graduate student, developed a high-precision phase detection algorithm. Combined with electronically controlled 100 MHz sound waves, which control the diffraction and frequency-shift of the etching laser, these MIT inventions allow rapid and precise patterning over large surface areas.

The bar is not yet set on the low limit of what can be accomplished by standard interference lithography. MIT's new invention could help advance the entire industry due to its foundation in widely used lithography techniques. There is still a long way to go before the IC industry needs to worry about building quantum circuitry, and that road is paved by the ever-shrinking die and multiplying core numbers.

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So you're saying...
By Cheapshot on 7/11/2008 8:54:52 AM , Rating: 2
they can do the same job only better?

RE: So you're saying...
By AnnihilatorX on 7/11/2008 9:12:27 AM , Rating: 3
Rather than requiring a completely new lithography, i.e. Extreme Ultraviolet Lithography, which is very expensive to implement (need to convert all existing fabs); The research here allows the existing lithography technology (Deep Ultraviolet Lithography) to be enhanced (through cheaper upgrades than upgrading the lithography process); thus postponing or even eliminating the need for the next generation Extreme Ultraviolet Lithography

RE: So you're saying...
By amanojaku on 7/11/2008 9:27:02 AM , Rating: 2
My guess is the yields would be poor for CPUs made by "Extremely UltraViolent Lithography!" ;)

RE: So you're saying...
By gyranthir on 7/11/2008 9:33:10 AM , Rating: 2
Right and the farther they shrink this, it will run cooler, take less energy, and be able to be combined with a greater number of processor cores into a greater whole.

In the space where you could fit 4 processor cores at 65mn processor you could fit ~16-24 25nm cores.

RE: So you're saying...
By Cheapshot on 7/11/2008 10:09:11 AM , Rating: 2
But I thought the problem was also from electric charge jumping to other wires due to how close they are. Then frying the circuitry and blowing out the silicone.

Has that problem been addressed to allow this further shrink? Was that the High K gate thing I read about before?

RE: So you're saying...
By Believer on 7/11/2008 10:29:43 AM , Rating: 2
The leakage through low gate dielectrics at transistor level is not the same thing as electromagnetic interference, as the latter you could solve with simple decoupling.

RE: So you're saying...
By jtemplin on 7/11/2008 11:07:38 AM , Rating: 5
Silocone blowouts are a concern of porn stars, not semiconductor manufacturers.

RE: So you're saying...
By willssi on 7/15/2008 2:26:30 PM , Rating: 2
While I don't think the below method is compatible, or even in the same ballpark, with the MIT method outlined above; IBM's method of insulating interconnects with vacuum is certainly interesting.

(sorry for the convoluted grammar)

RE: So you're saying...
By masher2 on 7/11/2008 10:34:27 AM , Rating: 3
> "In the space where you could fit 4 processor cores at 65mn processor you could fit ~16-24 25nm cores"

More like 27, assuming a flat shrink. Of course, its never that simple, as gates and other features change relative size as their size decreases.

RE: So you're saying...
By SiliconJon on 7/14/2008 2:59:36 PM , Rating: 2
Yeah, just on size alone - ignoring other factors - it's a real estate yield improvement of a 6.76 factor in a two dimensional design.

RE: So you're saying...
By Jedi2155 on 7/11/2008 9:42:31 AM , Rating: 2
I think they will get there in either case mainly because its the final limit. Of course you could be right and someone figures out a better way to do things and dump it altogether just like a 4 GHz P4....

RE: So you're saying...
By TennesseeTony on 7/11/2008 4:43:36 PM , Rating: 2
Yes, they've improved upon an existing process, kinda like when you convert your Spearmen/Pikemen into Riflemen/Infantry, or your Knights into Cavalry, or your Catapults into Artillery.

It's one small step for chip, one giant leap for chip's makers.

By Pottervilla on 7/11/2008 11:10:04 AM , Rating: 2
They scaled down, down, down and the transistors went higher.

Does anyone else recognize the sentence pattern of this?

"I modded down, down, down, and the flames went higher." -- Sven Olsen

RE: Quote
By aftlizard on 7/11/2008 11:15:59 AM , Rating: 2
Why yes I do:

I fell into a burnin' ring of fire.
I went down, down, down,
And the flames went higher.
And it burns, burns, burns,
The ring of fire.
The ring of fire.

Johnny Cash-Ring of Fire 1963

RE: Quote
By HVAC on 7/11/2008 11:49:08 AM , Rating: 3
I think Johnny was singing about his hemorrhoids.

RE: Quote
By TETRONG on 7/11/2008 1:46:30 PM , Rating: 2
Could of been the Meth too

RE: Quote
By Shadowself on 7/11/2008 3:16:39 PM , Rating: 3
Actually, the song was written by June Carter (who much, much later married Cash). It was supposedly about her thoughts and feelings on falling in love with Cash, and the hazards associated with doing so.

Not as great as it sounds
By glitchc on 7/11/2008 9:41:25 AM , Rating: 2
Being able to cut feature sizes that small is great, but it is only one part of the solution. One of the major problems Intel faced at 45nm were tunneling effects occurring in regular semiconductor substrate. Developing new materials with higher dielectric constants is essential to be able to utilize such feature sizes.

RE: Not as great as it sounds
By Believer on 7/11/2008 10:23:41 AM , Rating: 2
Aye, but Intel have had their new hafnium dioxide "high-k" metal gate dielectrics only since 45nm (as a result of the problems you mentioned). So I would think they can keep up with the pace of the shrinking dies for a while longer at least.

If not, there's always zirconium dioxide (ZrO2) or titanium dioxide (TiO2) and other materials to use instead, with even higher dielectric constants.

RE: Not as great as it sounds
By PandaBear on 7/11/2008 1:17:16 PM , Rating: 2
The all new Intel Core Oct processor with Titanium Dioxide, a high tech with self cleaning technology.

“So far we have not seen a single Android device that does not infringe on our patents." -- Microsoft General Counsel Brad Smith

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