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The first official die shot of "Penryn"

Intel's high-k, metal gate transistors replace the silicon-based elements of the transistor with hafnium and metal composites
Intel confirms new details on "Penryn" family: SSE4, high-k dielectrics, metal gate transistors

A little more than six months ago we wrote an editorial about Intel's future technology after Core 2 Duo, titled "Life After Conroe."  Life after Conroe inches closer, but, in the meantime, more details on the architecture are available today.

DailyTech had the opportunity to chat with Mark Bohr, Intel Senior Fellow, and Steve Smith, Intel Vice President DEG Group Operations, about the upcoming CPU design.

The primary focus of Intel's next-generation process technology is PenrynPenryn is the specific codename a 45nm mobile shrink of the Conroe core, but the codename may also be used to describe the entire product family.  Early last year Intel announced it would optically shrink to the next process node every two years.  Staggered one year later, the company would also announce a new microarchitecture.  This philosophy of shrink followed by architecture revision will undergo its first real milestone with the node shrink from 65nm to 45nm Penryn.  One year after the 45nm Penryn shrink, Intel is also expected to announce its next-generation microarchitecture successor, Nehalem

Intel claims the upcoming Penryn will fit 410 million transistors for the dual-core model, and 820 million transistors for the quad-core variants -- dual-core Conroe utilizes just 298 million transistors.  Intel's 45nm SRAM shuttle chip, announced last year, had a little over 1 billion transistors and fit on a 119mm^2 package.  However, the initial Penryn quad-core processors will use a multi-die packaging, so it's realistic to expect only 410 million transistors per die at launch.

The optical shrink allows the engineers to boost clock speed, but the additional real estate means the company can put more logic on the processor as well. "Most of that transistor savings is spent on increasing the cache over Core 2" added Smith.

Conroe added additional SSE instructions at launch, but Intel claimed at Fall IDF 2006 that SSE4 was specifically reserved for Nehalem.  Intel's guidance for Penryn claims the family will feature "New Intel SSE4 instructions expand capabilities and performance for media/HPC applications."

When asked about the effects of SSE4 on Penryn, Smith responded to DailyTech claiming "We're seeing excellent double digit performance [percentage] gains on multimedia applications."

Penryn is still not without its mysteries; a primary concern for enthusiasts is motherboard and socket support.  Penryn will launch on Socket 775 -- meaning existing motherboards can physically harbor the new CPU,  but electrically might not. "Motherboard developers will have to make some minor changes to support [Penryn]. We can't guarantee that a person could just plug the chip into every motherboard on the market today."  However, Smith also claimed the Penryn boot test that grabbed so many headlines last week occurred on unmodified hardware that included a notebook, several desktop motherboards and several server motherboards.

The lithography process for Penryn, dubbed P1266, is not just a shrink from 65nm to 45nm.  Perhaps the most significant advance on P1266 is the use of high-k dielectrics and metal gate transistors.  In a nutshell, the polysilicon gate used on transistors today is replaced with a metal layer and the silicon dioxide dielectric that sits between the substrate and the transistor is replaced by a high-k dielectric. 

Intel's push for high-k dielectrics and metal gate transistors may be more significant than the node shrink.  Intel's guidance documentation claims with the new high-k dielectric, metal gate transistors offer a 20% increase in current, which can translate to a 20% increase in performance.  When the new transistor technologies run at the same current and frequencies as Core 2 Duo processors today, translates to a 5-fold reduction in source-drain leakage and a 10-fold reduction in dielectric leakage.

"The implementation of high-k and metal gate materials marks the biggest change in transistor technology since the introduction of polysilicongate MOS transistors in the late 1960s" claims Gordon Moore, Intel co-founder attributed with coining "Moore's Law."

Intel would not reveal the materials used in its metal gate technology, though Smith announced that the dielectric is hafnium based.  Hafnium dioxide has been the leading candidate to replace silicon oxide inside academia for years.  A different material is used for PMOS and NMOS gates.

Intel's lithography roadmap no longer ends at P1268, the 32nm node.  Earlier today Intel revealed its 22nm node, dubbed 1270, slated for first production in 2011. 

Smith closed our conversation with "In 2008, we'll have Nehalem."


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AMD's response
By feelingshorter on 1/27/2007 1:32:35 AM , Rating: 2
I wonder what's AMD's response to this? I'm running on a AMD 64 3000+, and have been a AMD fan for years, since they give better bang for your buck. But now, with rising electricity costs and power requirements for PCs, I don't see any AMD CPU that can even touch C2D, much less this. AMD doesn't even overclock anywhere near a C2D. From what i can understand, overclocks on this new Intel CPU in 2008 will be even better than current C2D. Where does AMD stand?




RE: AMD's response
By Hare on 1/27/2007 3:24:07 AM , Rating: 3
quote:
have been a AMD fan for years, since they give better bang for your buck.

True for the low-end processors. With mainstream and high-end processors the situation is a lot different. Check out some benchmarks at Anandtech. Even E6300 is kicking AMDs flagship models butt in some tests. The E6300 has more or less the same performance as the 4600+ but in media encoding etc the conroe really shines.

If you are an overclocker you should know that even a child can run a E6300 >3Ghz. A 3Ghz E6300 is ~25% faster than FX62, for ~180$! Even without overclocking the E6300 is pretty much tied with the 5000+. Talk about performance and value!


RE: AMD's response
By jtesoro on 1/27/2007 6:07:05 AM , Rating: 2
I'm not an overclocker, but I'll be thinking about it when I get a new system with a Core 2 Duo in a couple of months. I thought I read somewhere that you'd need to switch fans to bump up the clock speed much higher than what the C2D was rated for. If so, the overclock process gets a tad bit trickier.


RE: AMD's response
By semo on 1/27/2007 9:18:32 AM , Rating: 3
just get an e4300 and run it at 1:1 ratio with ddr2-800 memory and stock cooling.
http://www.anandtech.com/cpuchipsets/showdoc.aspx?...


RE: AMD's response
By jtesoro on 1/27/2007 9:17:37 PM , Rating: 2
Wow, that is such a great option! The E4300 just jumped to the top of my list.


RE: AMD's response
By Viditor on 1/27/2007 6:53:57 AM , Rating: 3
quote:
I wonder what's AMD's response to this?


It's this:
"IBM today announced it has developed a long-sought improvement to the transistor - the tiny on/off switch that serves as the basic building block of virtually all microchips made today...Working with AMD and its other development partners Sony and Toshiba, the company has found a way to construct a critical part of the transistor with a new material, clearing a path toward chip circuitry that is smaller, faster and more power-efficient than previously thought possible...The technology, called "high-k metal gate," substitutes a new material into a critical portion of the transistor that controls its primary on/off switching function. The material provides superior electrical properties compared to its predecessor, enhancing the transistor's function while also allowing the size of the transistor to be shrunk beyond limits being reached today"

http://biz.yahoo.com/bw/070127/20070126005722.html...

Deja Vu all over again...

"IBM has inserted the technology into its state-of-the-art semiconductor manufacturing line in East Fishkill, NY and will apply it to products with chip circuits as small as 45 nanometers (billionths of a meter) starting in 2008"


RE: AMD's response
By penter on 1/27/2007 8:23:57 AM , Rating: 2
Mayby it is more a response of intel to amd.
IBM and AMD have allready developped something similar for 45nm. Allthough it used to be called ultra-low-k interconnect dielectrics. Too bad they are only going to use it in 2008.

source: http://home.nestor.minsk.by/computers/news/2006/12...


RE: AMD's response
By DallasTexas on 1/27/2007 9:58:58 AM , Rating: 2
Do you feel pretty confident about AMD's response (OK, riding on IBM's coat tails) to this breakthrough advance in lithography?

It seems you were pretty confident back about a year ago and it did not quite pan out..
http://www.dailytech.com/Article.aspx?newsid=550&c...


RE: AMD's response
By Viditor on 1/27/2007 11:25:49 AM , Rating: 2
quote:
Do you feel pretty confident about AMD's response (OK, riding on IBM's coat tails) to this breakthrough advance in lithography?


Ummm...I just posted a news story.
I have no idea where you get a question of confidence from.

quote:
It seems you were pretty confident back about a year ago and it did not quite pan out..


If you want to dispute the news story by pointing out that I make mistakes, let me help you out...
I make a lot of mistakes! :)
This was a good example of ideas that did not pan out completely...but let's look at what I actually said:

"1. most people are dubious that the 4-issue core (which is their main advantage) will be able to be utilized to it's full extent"

Well, that's quite true...I don't know of an OS/app mix that actually allows C2D to retire 4 issues/clock...certainly nothing very common.

"2. Realise that in the server sector, the FSB will still be a bottleneck"

That is also true as is evidenced by Opteron's superior scalability over Cloverton...

"Here is a first indication that quad core Xeon does not scale as well as the other systems. Two 2.4GHz Opteron 880 processors are as fast as one Xeon 5345, but four Opterons outperform the dual quad core Xeon by 16%. In other words, the quad Opteron system scales 31% better than the Xeon system"
http://tinyurl.com/2cgnj8

"3. Note that while AMD has made only modest gains in the mobile sector (from ~3% to ~15% in the last year), the Turion X2 being released in April will use DDR2 and use the new SiGe process, thus decreasing it's power usage to at least that of Yonah (and it will be 64 bit compared to Yonah's 32 bit). "

This is part of where it fell down...while AMD has continued to gain marketshare in mobile every quarter, I have a feeling that the new SiGe process had problems and wasn't used (I think this mainly due to the lack of overclockability).
It is possible we will see it in Barcelona, but who knows?

"4. Also note that 64 bit Vista is due for Gold release in October"

Let's not even go there...

"5. The new SiGe process will allow AMD's desktop parts to exceed 3 GHz this year, even at 90nm
6. AMD's 65nm parts will start to ship in Q3/Q4"


Oops...though the 65nm certainly shipped on time, SiGe has yet to show itself.

"Intel may come close to catching up, but they won't take the crown again until well into 2007...if at all"

So who knew that C2D would be so good? It's like all of those people here who say that a 40% improvement over Cloverton is impossible, and those who think it's inevitable...this post should be a lesson to you guys!
Skepticism is good for everything.


RE: AMD's response
By crystal clear on 1/27/2007 10:14:53 PM , Rating: 3
After ALL this, SUN a long time partner of AMD switches over to INTEL.

The realities of the market speak for themselves.


RE: AMD's response
By Viditor on 1/28/2007 5:03:38 AM , Rating: 1
quote:
SUN a long time partner of AMD switches over to INTEL

Not really...they are ADDING Intel because they finally have a worthy processer.
Funny how people keep missing that...:)


RE: AMD's response
By crystal clear on 1/28/2007 7:31:13 AM , Rating: 2
Not really-its much more than simple worthy processor,
its a long term agreement that goes very far ,
read this to get an idea of what it is about.
Then you will notice AMD is slowly to be put aside- A downgraded relationship.

Quote-

Sun(SUNW) And Intel(INTC) Announce Landmark Agreement
Sun Microsystems, Inc. (Nasdaq: SUNW) and Intel Corporation today announced a broad strategic alliance centered on Intel's endorsement of the Solaris Operating System (OS) and Sun's commitment to deliver a comprehensive family of enterprise and telecommunications servers and workstations based on Intel Xeon processors. The scope of the agreement spans Solaris, Java and NetBeans software and Intel Xeon microprocessors, as well as other Intel and Sun enterprise-class technologies. The alliance also includes joint engineering, design and marketing efforts.


As part of today's announcement, Intel is embracing Solaris as a mainstream OS and the enterprise class, mission critical UNIX OS for Intel Xeon processor-based servers. Intel also endorses Sun's Solaris, Java and NetBeans products and will actively support the OpenSolaris and open Java communities from which they continue to evolve.

Sun is committed to leading on performance and energy efficiency in its server product line. After a comprehensive evaluation of industry platform solutions, Sun has decided to complement its current offerings with platforms based on Intel Architecture optimized for Solaris beginning in the first half of 2007. Sun believes Intel's model of alternating new microarchitectures with new process technologies on an annual basis will offer outstanding building blocks for Sun's customers.

Sun plans to deliver a comprehensive family of Intel-based systems with uni-, dual- and multi-processor based servers and workstations supporting Solaris, Windows and Linux. Intel and Sun will also collaborate around greater than four processor scale-up systems optimized for the Solaris OS.
..................................

http://technology-news-earnings.blogspot.com/searc...


RE: AMD's response
By Viditor on 1/28/2007 7:41:27 AM , Rating: 2
quote:
Then you will notice AMD is slowly to be put aside- A downgraded relationship


Are you kidding?
They are just releasing even newer Opteron products!
http://www.sun.com/aboutsun/pr/2007-01/sunflash.20...

SANTA CLARA, Calif. January 9, 2007 Sun Microsystems, Inc. (NASDAQ: SUNW) today announced the fastest blade server on the planet, in addition to the first subscription service that enables blade customers to keep their datacenters at peak performance and efficiency at half the cost of traditional acquisition methods. Posting three new performance world records, the Sun Blade X8420 server module and the Sun Refresh Service set a new standard for 4-socket servers, especially when combined with the Solaris 10 Operating System (OS), the most advanced operating system on the planet

The only reason for the Sun/Intel deal is to expand their vendors (the same as IBM, Dell, and HP have).
It also gets Intel on board with Solaris...
I think you're looking at this through Blue coloured glasses...


RE: AMD's response
By crystal clear on 1/28/2007 9:49:18 AM , Rating: 2
quote:
Then you will notice AMD is slowly to be put aside- A downgraded relationship

Unquote-
You will see/read on this, (in future )about this.
For now I put it on hold.

In the mean time some google news for you-

Quote-
Super-secretive Google had its insides exposed this week by Intel's amateur blogger and server chief Pat Gelsinger. The executive claims that Intel's server division has won back Google's business from AMD. IBM, HP, Dell, Sun Microsystems and Rackable must find this revelation curious.

Intel's white box server business receives little attention. The chip maker crafts a few different types of systems and will ship them to interested parties. It tends, however, to avoid stealing significant sales from its largest customers.

On the Google front, Intel went out of its way to steal such business. It produced a bespoke server line full of low-power, low-cost components that matched Google's demanding specifications.

Intel's server gurus "have been maniacal as we designed a unique board for them, developing a unique memory module with them, working every angle of the cost equation and engaging with our sales teams to get the business," Gelsinger wrote on his internal Intel blog, according to one of CNET's few non-Second Life reports.

http://www.theregister.co.uk/2007/01/26/intel_goog...




RE: AMD's response
By Viditor on 1/28/2007 10:52:42 PM , Rating: 2
crystal, you really have to stop taking everything Gelsinger writes as Gospel...
For example, just 2 days after the article you reprinted was posted, this was posted:

"Rumors of a full-on switch from AMD to Intel chips have forced Google to emerge from its warm, creepy secrecy cocoon. Contrary to claims from Intel, Google has not experienced Xeonmania and elevated Intel to favored supplier status. Rather, it's just got a few Xeons laying around its data centers"

http://www.theregister.co.uk/2007/01/28/google_amd...


RE: AMD's response
By cheetah2k on 1/29/07, Rating: 0
RE: AMD's response
By crystal clear on 1/29/2007 2:58:31 AM , Rating: 2
Great response-I like it -"ITS ORIGINAL"
A spontanous response I think.


See this Vedeo-
"Getting a look at Intel’s new 45nm fab"

http://scobleizer.com/2007/01/26/getting-a-look-at...

The second one(vedeo)is more interesting.

Also-
I had this,but Apple had it chopped out-really fast.

Leaked: Screenshots of OS X Leopard Terminal, Parental Controls, More


I had posted it on DT few days ago.

Apple Under Fire for Ambiguous Accounting Claims
Tuan Nguyen (Blog) - January 25, 2007 8:27 AM


"The Apple show"


RE: AMD's response
By crystal clear on 1/29/2007 3:08:03 AM , Rating: 2
You are right-Accepted.

Intel CEO Paul Otellini sits on their board(Google) so
such leaks come under intense scrutiny.






RE: AMD's response
By crystal clear on 1/28/2007 10:07:44 AM , Rating: 2
On Friday, Bank of American Equity Research analyst Sumit Dhanda wrote in a note to clients that his checks within the supply-chain in the technology industry indicated that Sun would start using Intel chips in servers that would be available to customers in late 2007.


"Development is currently taking place at the engineering level, with expectations for volume production sometime in late 2007," Dhanda wrote.

http://www.eweek.com/article2/0,1895,2086186,00.as...



RE: AMD's response
By Khato on 1/27/2007 3:28:17 PM , Rating: 2
I find it somewhat sad that IBM is touting this like it's some new innovation that they got to first. I do wonder how well their planned integration into their 45nm process will go though. Just because Intel was able to get their first product for the 45nm node to work on the first stepping doesn't mean it's easy - Intel had first high-k gate dielectric transistors in lab in Nov '03, so process engineers have had plenty of time to tweak it into production.

One curiosity in that press release, nothing is mentioned about the previously touted low-k interconnect dielectrics and immersion lithography. Would be rather humorous if there were some incompatibility between the high-k gate dielectric/gate metal and the immersion lithography process.


RE: AMD's response
By JackPack on 1/27/2007 4:14:00 PM , Rating: 4
Based on the timing of the news, IBM is basically saying "Me too! Me too!"


RE: AMD's response
By Viditor on 1/28/07, Rating: -1
RE: AMD's response
By Khato on 1/28/2007 2:32:47 PM , Rating: 2
Ayup, they're three completely different technologies, which is why I'm ever very careful to label the high-k as gate dielectric and low-k as interconnect dielectric. There shouldn't be any problem combining the two different dielectrics seeing as how they'd have limited contact points. But the gate metal might not like the low-k interconnect dielectric, or water - highly improbable, but it would be humorous.

Heh, Intel behind again? I guess if you go back far enough, IBM had a manufacturing technology lead. I somewhat doubt that there's much difference between the respective low-k interconnect dielectrics, while Intel's high-k dielectric is most probably quite superior.


RE: AMD's response
By Viditor on 1/28/2007 6:26:40 PM , Rating: 2
quote:
There shouldn't be any problem combining the two different dielectrics seeing as how they'd have limited contact points

That's not my point...I am dubious that AMD will have both processes ready together in time for 45nm production and still have good yields.


RE: AMD's response
By ChipDude on 1/27/2007 11:48:07 PM , Rating: 3
Me Too Me Too, Me toooooooo...

If IBM had anything to annouce they would have annouced in December at IEDM. IBM has a long track record of beating its chest every December trying to prove they are still the leader in silicon. Sad fact is they have one fab making game chips and CPUs to the tune of 20-50 million units.

TI, TSMC, Samsung, and INTEL are for more relevant in silicon then IBM is anymore


RE: AMD's response
By Viditor on 1/28/2007 5:21:29 AM , Rating: 1
quote:
If IBM had anything to annouce they would have annouced in December at IEDM

You mean like Intel's announcement...no, wait.
Fact is that AMD had 2 presentations at IEDM on HK/MG...and that development is a partnership with IBM.

quote:
Sad fact is they have one fab making game chips and CPUs to the tune of 20-50 million units

Well thank goodness they stopped with those pesky Power chips for servers...leading all benchmarks can be tiring. No, wait...they didn't!
You should also note the fact that they have production rights at Fab 36 and Fab 30/38. This was part of the original deal.


RE: AMD's response
By Khato on 1/28/2007 2:37:51 PM , Rating: 2
quote:
You mean like Intel's announcement...no, wait.


So now Intel needs to tout it's prior technological achievements at every conference in order to keep in the lead? I would have thought that a few announcements soon after the fact would be enough, such as those listed at the bottom here:

http://www.intel.com/technology/silicon/high-k.htm


RE: AMD's response
By Viditor on 1/28/2007 6:21:04 PM , Rating: 1
quote:
So now Intel needs to tout it's prior technological achievements at every conference in order to keep in the lead?

No, I think that announcing (or not) at IEDM means absolutely nothing...that was my point!


RE: AMD's response
By vrbbmf on 1/28/2007 11:14:31 PM , Rating: 2
any fanboi who went for AMD's ad blitz hawking "more bang for buck" and "cycles per second don't tell the whole story" when the truth was AMD couldn't get catch up, needs to be puzzled...
truth is, there are two major differences where Intel and AMD are concerned;
Intel s the undisputed industry leader and has this to lose.
AMD is the runner up and like Avis must try harder.
the whole "competition" thing is getting tired,and AMD is beginning to look alot like Apple in It's vs Microsoft role, who recently dropped the Computers from the name Apple Computers to become Apple Inc. A true indication of intent if I ever saw one.
I'm thinking AMD may want to learn GPU secrets from ATi...make some new kind of slower video card with "more bang for buck" I wonder if it would work twice. Given the right sized ad budget, it might, but I hope I don't get the chance o find out


WOW WOW WOW WOW
By ChipDude on 1/27/2007 11:35:12 PM , Rating: 2
Can you believe it INTEL has pulled the rabbit out of the hats Ladies and Gents!

They have annouced the biggest revolution in microelectronics since the polysilicon gate/SiO2 transistor used for the last 30 years.

I got to only laugh at them jokers on the East Coast. INTEL was brilliant. Let IBM come tell all the wonderfuly things on their next generation 45nm. Lower K backend ( small patatoes), SOI ( same thing they have done on the last three generations ), SiGe strain ( copied INTEL), and immersion ( talk about expensive and yield killing new litho).

It was interesting how INTEL said nothing at IEDM..

Now what do they do, got fully fuctional Core2 45nm CPUs fabricated with HiK and Metal Gate. Got 3 factories getting equiped to ramp 200million plus in 2008.

What IBM, TI and others annouced is old news. All of them have annouced HiK already in papers making individual devices all with various issues like Vt pinning, mobility degradation. All them papers talked about all the problems and how they weren't ready for prime time manufactuing. Looks like them boys in East Fishkill are going to be burning some serious midnight oil for the next year to catch up.





RE: WOW WOW WOW WOW
By flipsu5 on 1/28/2007 5:47:47 AM , Rating: 2
Lower K backend is the biggest deal for performance, since it affects RC delay.

Immersion lithography at 45 nm is more useful for chip shrinks. The cost is high but it can extend further than dry. Toshiba is already using immersion lithography for 56 nm Flash.

The high-k option was always posed as an option. They could have done it without high-k, but since they already got the equipment, why waste?


RE: WOW WOW WOW WOW
By Viditor on 1/28/2007 7:35:17 AM , Rating: 2
High-k metal gates for Penryn has been on the roadmap for almost 2 years now...


RE: WOW WOW WOW WOW
By ChipDude on 1/28/2007 11:08:52 AM , Rating: 2
"Lower K backend is the biggest deal for performance, since it affects RC delay"

LOL let me dumb it down. LowK is like streamlining car to reduce wind resistance. The engine matters much more thats the transistors. THe problems is that as we scaled gate oxide it leakage has increased orders of magnitude. Everyone has been looking for a suitable HiK material for the last 5 years. To find one that doesn't cause Vt pinning nor mobility degredation is a huge feat. I'm sure now that INTEL has annouced and committed 7+ billion of capital to the process everyone knows it can be done. Thus IBM will surely find the secret combination too but they will be late. Doing HiK metal gate isn't as simple as just adding a few tools. I'll supsect a lot of things change that means you can't just change the process and take the same Barcelona and run it. That means it'll be a few years before you see it in any AMD chip.

I got lost.. how many of those great Powerchips do they sell a year? Few hundred thousand... opps maybe a few million WOW or wow.


RE: WOW WOW WOW WOW
By flipsu5 on 1/28/2007 7:14:22 PM , Rating: 2
High-k is a process solution to an issue that does not require a process solution. A lower gate-to-channel voltage on demand would do the job equally well.


RE: WOW WOW WOW WOW
By ChipDude on 1/28/2007 11:48:42 PM , Rating: 2
Silly silly silly, have you taken an undergraduate device physics course and understand KT/Q? Vt can't be lowered anymore at room temperature without excessive leakage as you will lower the barrier between source and drain. Anything much lower then 400mV and you can't turn the transistors off. Thus you can't just reduced the drain voltage as Vdd-Vt won't be enough to dry that lowK backend.

Thus to get good drive current and minimum leakage you need Vdd about 1 volt or so. Any lower and you get really low performing transistors. Of course in sleep/slow mode you can do all you want reduce Vdd but then you have this thing called SRAM stability to deal with.

High K / Metal gate is as close to having your cake and eating it to!


RE: WOW WOW WOW WOW
By flipsu5 on 1/29/2007 12:18:38 AM , Rating: 2
quote:
Silly silly silly, have you taken an undergraduate device physics course and understand KT/Q? Vt can't be lowered anymore at room temperature without excessive leakage as you will lower the barrier between source and drain. Anything much lower then 400mV and you can't turn the transistors off. Thus you can't just reduced the drain voltage as Vdd-Vt won't be enough to dry that lowK backend.

Thus to get good drive current and minimum leakage you need Vdd about 1 volt or so. Any lower and you get really low performing transistors. Of course in sleep/slow mode you can do all you want reduce Vdd but then you have this thing called SRAM stability to deal with.

High K / Metal gate is as close to having your cake and eating it to!


you and I are talking about differnt voltages because I agree with the Vth statement and sleep mode.

I am talking about after the conducting channel is formed under the gate, the source and drain nodes should not have to be at a voltage level which results in significant tunneling current.


RE: WOW WOW WOW WOW
By Khato on 1/29/2007 2:19:14 AM , Rating: 2
Well, how exactly would you propose changing the source/drain voltage after the channel's formed and still have that transistor drive whatever logic's next?


RE: WOW WOW WOW WOW
By flipsu5 on 1/29/2007 10:25:57 AM , Rating: 2
There are apparently lots of ways of doing it. You may think of how to avoid turning on transistors near ground, which drive nothing.


RE: WOW WOW WOW WOW
By Khato on 1/29/2007 12:11:26 PM , Rating: 2
There are probably lots of ways that graduate students and professors dream up in an academic setting that are absolutely worthless for practical applications, sure.

As to actual designs, uhhhh, there aren't all -that- many transistors that are just sitting around not driving anything. (Yes, there are some put in for making logic corrections after base tapeout.) But for actual active logic transistors, how would you propose reducing both gate and channel leakage? Changing gate to channel voltage is going to adversely affect the output voltage, which results in greatly reduced drive current and hence speed of the following logic.


RE: WOW WOW WOW WOW
By flipsu5 on 1/29/2007 7:09:44 PM , Rating: 2
Yeah a lot of published solutions are pretty useless. But I am sure it's already exploited to some degree (maybe not aggressively) in CPU designs.

Nothing has to be disturbed, not Vg, not Vds (so your drive is okay). The thing to note is, the gate leakage is dominated by where Vg>>Vd~Vs~0.


RE: WOW WOW WOW WOW
By Khato on 1/29/2007 8:37:16 PM , Rating: 2
Ayup, and considering that Vd is typically Vg for whatever logic comes next, well, it becomes difficult to do much. There is -always- going to be a Vdd to Vss voltage differential across a gate in typical CMOS logic that's in an active state (not sleep tranistor'd off.)

Lowering the Vdd to Vss voltage is a favored way to decrease leakage, but has adverse performance characteristics. A process change to a different gate dielectric is the only practical way to reduce gate leakage without sacrificing performance. There has been a -lot- of work put into this process change, Intel has taken their time (about three years) since first lab success to get everything right.

Mmmm, 10x reduction in gate leakage. Possible 5x reduction in source-drain leakage or 20% faster switching speed. And then what's oddly missing from DailyTech's article (can be found on Intel's 45nm silicon technology page), 30% reduction in transistor switching power.


RE: WOW WOW WOW WOW
By flipsu5 on 1/29/2007 8:58:40 PM , Rating: 2
The process is not without compromise itself, not everything is "right". The interface with the silicon is still key, and is effectively still native oxide.

If the leakage by itself were so significant, power reduction should be much more aggressive, but it's about par. 5-10X but power is about even, assuming doubling transistors, it still appears limited.

Not to say it is not a great thing. It's a good change, and impressive work. What is the next step now? High-k thickness doesn't scale like SiO2, since there is an unscalable interface layer with silicon. They must be working on next-generation gate dielectric. Follow the DRAM makers.


RE: WOW WOW WOW WOW
By Khato on 1/30/2007 2:59:49 AM , Rating: 2
Hrmmmm? Interface with the silicon is still native oxide? Even if they're using a halfnium oxide dielectric rather than halfnium silicate, there wouldn't be any interface layer of native oxide. Gate dielectric deposition is a -very- well controlled process.

Sure, leakage isn't as much of a problem at 65nm as it was at 90nm, primarily due to smarter design (halt states, sleep transistors.) But 65nm was never anticipated to be a problem node for leakage, the geometries weren't that bad yet. Reducing leakage at 45nm rather than increasing is great, that 5-10X means reduction of idle power from the ~22W current down to 2-4W. And 30% decrease in gate switching power brings, say, 53W (just a guesstimate based off 75W total for 3GHz core 2 duo) down to 37W. So, now your 75W CPU becomes around 40W.

Believe there was an eetimes article a bit back that quoted one of the senior process engineers at Intel stating second gen high-k gate dielectric was in the works, probably for the 32nm node.


RE: WOW WOW WOW WOW
By flipsu5 on 1/30/2007 3:33:23 AM , Rating: 2
The SiO interface is desirable for the mobility since it is as close to native oxide as possible, it is deliberately retained, albeit sub-nm thickness.

Gate leakage is a more an issue for active CPUs not standby. Pentium M is already 5 W idle:http://www.macinfo.de/archiv/2004-09.html

I don't know where you get your figures.

TDP is not changing for dual cores going to 45 nm:
http://xtreview.com/addcomment-id-1165-view-intel-...



RE: WOW WOW WOW WOW
By ChipDude on 1/30/2007 11:16:52 AM , Rating: 2
SiO2 buffer layer, really? Think thru what you said. Today we can't support a thinner electrical thickness and control leakage. Now you tell me you need a layer of Oxide then add some thicker HiK and get a thinner electrical oxide then a nitrided oxide... Sorry is that HiK have negative effecitive oxide thickness? If you add a buffer of oxide then you negate all the benifits of having HiK helping your eletrical TOX.


RE: WOW WOW WOW WOW
By flipsu5 on 1/30/2007 7:17:13 PM , Rating: 2
quote:
SiO2 buffer layer, really? Think thru what you said. Today we can't support a thinner electrical thickness and control leakage. Now you tell me you need a layer of Oxide then add some thicker HiK and get a thinner electrical oxide then a nitrided oxide... Sorry is that HiK have negative effecitive oxide thickness? If you add a buffer of oxide then you negate all the benifits of having HiK helping your eletrical TOX.


It's not that bad, there is some headroom.

The formula used is tsio2/ksio2+thfsio/khfsio+thfo2/khfo2=t(total)/keff . So the first two terms can be made as small as possible for higher keff. khfo2~25,khfsio~16,ksio2~4 roughly (varies in literature).

It's true that you don't get the SiO during gate dielectric deposition. It occurs during annealing. The degree of this oxidation is controllable to some extent (enough for many groups' satisfaction).


RE: WOW WOW WOW WOW
By Khato on 1/30/2007 12:19:55 PM , Rating: 2
I'm not involved in the process engineering, so I don't know exactly what method Intel's high-k process is using. Seeing as how it's a trade secret, I doubt anyone who does would post it. That said, what does the interface between dielectric and silicon have to do with electron mobility through the channel area? Part of the desirability of halfnium in my understanding was that it interfaced so nicely with silicon, the problem was always on the gate electrode.

Extended halt power for core 2 duo is 22/12W (available in Intel's datasheet.) Believe the 12W figure is for the 2MB. Either way, yes, gate leakage can be more of an issue when not in standby, depends upon the design.

Anyway, all those figures are based upon the current conroe at 3GHz. And even if you increase the figure by the amount of core logic increase going into wolfdale, you still only get 50W. Either way, at this point it's all just speculation anyway. Intel's current figures are just based on simulations since silicon isn't at speed. So even if that was an actual roadmap, Intel wouldn't have lowered TDP on it in the least.


RE: WOW WOW WOW WOW
By flipsu5 on 1/30/2007 7:44:26 PM , Rating: 2
quote:
Extended halt power for core 2 duo is 22/12W (available in Intel's datasheet.) Believe the 12W figure is for the 2MB. Either way, yes, gate leakage can be more of an issue when not in standby, depends upon the design.

Anyway, all those figures are based upon the current conroe at 3GHz. And even if you increase the figure by the amount of core logic increase going into wolfdale, you still only get 50W. Either way, at this point it's all just speculation anyway. Intel's current figures are just based on simulations since silicon isn't at speed. So even if that was an actual roadmap, Intel wouldn't have lowered TDP on it in the least.


Okay, I see. The clock speeds are going up again. Maybe performance per watt is more important to Intel. And in a laptop, even with a lower wattage CPU, the battery life is still killed by other non-optimized factors anyway (wireless, display).

quote:
I'm not involved in the process engineering, so I don't know exactly what method Intel's high-k process is using. Seeing as how it's a trade secret, I doubt anyone who does would post it. That said, what does the interface between dielectric and silicon have to do with electron mobility through the channel area? Part of the desirability of halfnium in my understanding was that it interfaced so nicely with silicon, the problem was always on the gate electrode.


I don't claim to know the Intel or IBM process, I am only familiar with the research work that has gone into it. When using the high-k, a great deal of effort is put into reducing traps and defects which limit the electron (or hole) mobility by unwanted scattering. A SiO interface helps mainly by separating Si from these defects, but obviously the tradeoff is this interface should be as thin as possible to avoid increasing the EOT.


RE: WOW WOW WOW WOW
By Khato on 1/30/2007 8:21:36 PM , Rating: 2
Ahhhh, makes a bit more sense now. I guess that if Intel is using a halfnium oxide, then the lattice that'd be formed would technically be, for one layer, both silicon oxide and halfnium oxide, haha. I'd guess past that point though it'd just be a halfnium oxide, since that's going to take care of all the boundary effects right there.

It'll be interesting to see exactly what's being done once it's in production and they can actually put out more information.


Why use high-k?
By flipsu5 on 1/27/2007 2:16:03 PM , Rating: 1
Intel had the option to not use high-k. The circuit design could be better, for example.

Penryn still consumes same power as Merom, scary to think if nothing was done to reduce power when scaling.




RE: Why use high-k?
By Khato on 1/27/2007 3:16:28 PM , Rating: 2
quote:
Penryn still consumes same power as Merom


Oh it does hrmmmm? I'm certain that's why there was this lovely little slide from IDF that stated CPU TDP in 1H'07 would be 1/2 of the value in '06, while in '08 it would be approximately 1/10 of the '06 value. Yeah... That really sounds like it's going to consume the same power as Merom.


RE: Why use high-k?
By flipsu5 on 1/27/2007 3:39:22 PM , Rating: 2
Penryn is way bigger than Merom. That explains why power hasn't gone down but leveled off.

http://www.computerpoweruser.com/editorial/article...

quote:
I'm certain that's why there was this lovely little slide from IDF that stated CPU TDP in 1H'07 would be 1/2 of the value in '06, while in '08 it would be approximately 1/10 of the '06 value.


This slide then should be advertised all over; it's not.


RE: Why use high-k?
By Khato on 1/27/2007 7:23:21 PM , Rating: 2
Yes, it is way bigger. About 96 million of the transistor count increase is from the extra 2MB L2 cache, leaving 23 million for L1 and core logic changes. As I'm certain you know, the L2 transistors have minimal power impact, so most of the size difference isn't going to do much with respect to power.

I no need to comment much on the validity of the link provided, seeing as how it says right in the link 'editorial' and it's a subscription required site. I far prefer scouring around for information from the source, it's not that difficult to do.


RE: Why use high-k?
By flipsu5 on 1/27/2007 8:20:20 PM , Rating: 2
quote:
I no need to comment much on the validity of the link provided, seeing as how it says right in the link 'editorial' and it's a subscription required site. I far prefer scouring around for information from the source, it's not that difficult to do.


It was a pro-Core architecture article. Not likely to try to put down the new processors. But you may want to translate this:
http://www.matbe.com/actualites/commenter/15262/in...


RE: Why use high-k?
By Khato on 1/28/2007 4:48:49 AM , Rating: 2
Well, I am quite curious as to where they got that TDP figure - heh, as with so many 'Intel confidential' things it shouldn't be known yet.

Anyway, going from 75 watts at 3 GHz to 57 watts at 4 GHz isn't a power decrease? Oh, and I believe that slide from IDF was in terms of constant performance or frequency purrhaps.


RE: Why use high-k?
By flipsu5 on 1/28/2007 5:50:38 AM , Rating: 2
In the first link, the TDP for Penryn was cited as 35 W which is same as Merom. That was what I referred to earlier.

The TDP is independent of GHz, keeping in mind that TDP is not an actual power figure but a power design spec.


RE: Why use high-k?
By Khato on 1/28/2007 2:49:47 PM , Rating: 2
Ahhhh, quite true, quite true. I tend to associate the entire line with the mobile codename. But if you're talking about -just- the mobile processors, then sure, they aren't decreasing TDP. It's a thermal design spec that usually applies most accurately to the top frequency part, typically not lowered for the rest in order to encourage one cooling solution for the entire line. Which is why Penryn isn't lowering the TDP - far more friendly in the laptop space to not have to do a redesign, and especially to be able to use a Merom in a laptop designed for Penryn.

That interoperability isn't quite as important in desktop/server space as is getting the cost of cooling solutions down further. Hence those thermal guidelines are far more in line with the actual characteristics.


high-k?
By penter on 1/27/2007 6:36:06 AM , Rating: 2
I thought that AMD allready had that technology. High-k just seems to ring a bell to me.




RE: high-k?
By DallasTexas on 1/27/2007 9:39:25 AM , Rating: 2
Yep, AMD has hi-K dielectric. They just have to spin their marketing messages that they have "Hyper- Dielectric".

It's all found here.
http://www.theregister.co.uk/2003/12/10/amd_dismis...


RE: high-k?
By SexyK on 1/27/2007 10:44:29 AM , Rating: 2
Uhh, that article explicitly says that AMD will not be using a high-k dielectric. In response to Penter's original post, you are thinking of low-k dielectrics. AMD introduced the use of low-k dielectrics along with its SOI implementation with the 130nm process. See question number 9 here: http://www.anandtech.com/showdoc.aspx?i=2242&p=2 and also further explanation here: http://www.chip-architect.com/news/2000_11_07_proc...

AMD has never used high-k materials, and apparently is not planning on using high-k materials any time soon.


RE: high-k?
By KristopherKubicki (blog) on 1/27/2007 10:52:57 AM , Rating: 3
Keep in mind, the low-k dielectrics are only for interconnects. High-k are used in transistors.


RE: high-k?
By SexyK on 1/27/2007 11:42:28 AM , Rating: 2
Understood - I did not mean to imply that AMD was using low-k dielectrics in the same manner Intel is incorporating high-k dielectrics. Was only responding to the comment that "high-k rang a bell" for the OP, and suggesting that he was probably recalling AMD's use of low-k dielectrics beginning with their 130nm process. Haven't had time to read all the announcements yet, but now it appears that perhaps AMD/IBM's new "ultra-low-k" process is similar to Intel's High-k, so I may have to correct myself in saying that AMD won't be using this technology if that proves to be true.


RE: high-k?
By JackPack on 1/27/2007 4:06:35 PM , Rating: 2
The two are not similiar at all. High-k dielectrics is for the transistor gates. Low-k is used to lower the capacitance between wires. You want the transistor gates to behave as much like a capacitor as possible and the wires to _not_ behave as capacitors. Hence, both high- and low-k dielectrics are important. IBM just announced news about high-k, but the window of opportunity for AMD has probably closed and their implementation of it isn't likely to occur until 32nm.


RE: high-k?
By Viditor on 1/28/2007 5:29:41 AM , Rating: 1
quote:
the window of opportunity for AMD has probably closed and their implementation of it isn't likely to occur until 32nm

I believe the article specifically states that they will be implemented in 45nm along with the ultra-low-k for the interconnects.


HT re enabled
By crystal clear on 1/27/2007 4:53:24 AM , Rating: 2
"Penryn is still not without its mysteries;"

Penryn cores will have HT re-enabled. -can Kristopher check
if this true.




RE: HT re enabled
By Goty on 1/27/2007 11:49:55 AM , Rating: 1
HT was never much of a performance boost for any of Intel's processors anyways. I think the other architectural changes/upgrades will far outshine HT.


RE: HT re enabled
By InsaneScientist on 1/27/2007 2:39:01 PM , Rating: 2
HyperThreading was primarily possible on the Pentium 4s due to the ulta long pipeline.

Also, HT didn't show performance gains across the board... in some scenarios (I.E. Gaming) it would actually provide a performace loss. It gave us the ability to process two threads simultaneously, with, occasionally (though rarely), up to 20% performance gains.
A true dual core processor, however, can handle the same two threads with roughly 80% performance gains (and that figure is fairly consistent), and never show any performance loss with single threads (compared to just one core being active).
Since the Core2 architecture is natively dual core (yes I know there are single core chips out there that are part of the Core 2 lineup, but they're, by far, in the minority) it can handle those two threads very well as things stand; however, most applications can barely handle two cores at this point, let alone more than 2 cores (or virtual processors, in the case of HT).

Add to that the fact that the operating system has difficulty differentiating between different cores and different logical processors, so it might assign the heaviest load to the same core's two processing engines, while the other core sits mostly idle, and you start seeing most of the drawbacks of HT without any of its benefits, except under certain (rare, for the normal user) scenarios.
(We saw most of these issues crop up with the Pentium 965, which was dual core and HT enabled, if you want to go check)


Between all that, and the difficulty (if not impossiblilty, I don't know) of implementing HT on Core2's micro architecture, I would be extremely suprised if we ever see HT again.

HT was a stepping stone to multi-core processing... not something to be used once we got there.


RE: HT re enabled
By cochy on 1/27/2007 3:08:56 PM , Rating: 1
quote:
Core2 architecture is natively dual core


AMD fanboys are going to hate you for using that word in a sentence describing Intel.


RE: HT re enabled
By Zandros on 1/27/2007 9:50:25 PM , Rating: 2
quote:
HyperThreading was primarily possible on the Pentium 4s due to the ulta long pipeline.


While explicitly HyperThreading might be suitable for the Pentium 4 only, other more shallow chips such as the Itanium 2 can and do employ mulithreading.

I think it not impossible to see some kind of multithreading on later revisions of the Core microarchitecture.

Anyway, will we see a full SSE4 implementation on the Penryn or not? The article is ambiguous to me.


AMD's response?
By ajfink on 1/27/2007 1:53:26 AM , Rating: 2
I think this bit of media attention is to offset the recent statements by AMD about "K8L." Barcelona & Co., if they prove to be as powerful as AMD has claimed, will provide more than enough competition for Penryn to begin with. I wouldn't doubt that there are already whiteboards in AMD labs with ideas for the next architecture scribbled on them. They don't want to get stuck with a lacking architecture again as they have with K8 vs. C2D.

But it doesn't so much matter who makes the better processor at the time, the bottom line is that we, the consumers, get to reap the benefits of this processor war, :)




RE: AMD's response?
By Regs on 1/27/2007 3:36:58 PM , Rating: 2
I think this is very true. Their marketing campaign is brutal and they are pretty much fighting and fending for every bit of realistate.

I might actually become an Intel fanboy if they keep up with these tech advancements. Like Anand said for the past 5 years it's been pretty boring and it looks like AMD poked a stick at a hornets nest. The only barrier I see now is DDR2 and DDR3. I've been running DDR for the past 3-4 years. I don't want to be upgrading to DDR2 and then DDR3 in the same year.


RE: AMD's response?
By Frallan on 1/28/2007 4:33:50 AM , Rating: 2
Hopefully it is true - but I am afraid that AMDs knee jerk reaction to buy ATI has taken waaaaay to much effort to consolidate. I belive that both ATI and AMD has lost about 6-12 months in development time by now. Hopefully I am wrong but the sad fact is that the AMD guys are n00bs in consolidating a major merger while Intels are Pros in that area.

Well hopefully AMD will pull a rabbit out of the hat or my trusty Opty 175 will (at the end of its useful life) be replaced by an Intel - and I want more competition not less.

If anyone have any info on the post acquisition consolitation process Id like to read about it.


New arrival
By SunAngel on 1/27/2007 12:23:02 AM , Rating: 1
quote:
Penryn will launch on Socket 775, meaning existing motherboards can physically harbor the new CPU, but electrically might not.


Expected.




RE: New arrival
By Hypernova on 1/27/2007 12:48:47 AM , Rating: 2
quote:
However, the Smith also claimed the Penryn boot test that grabbed so many headlines last week occurred on unmodified hardware that included a notebook, several desktop motherboards and several server motherboards.

Might just happen to be true.


RE: New arrival
By TheBeagle on 1/27/2007 8:47:37 AM , Rating: 2
There might be more to this than initially meets the eye. Consider the second evolution of the P965 motherboards from Gigabyte. If you look closely at the differences between the first version and the upcoming second version, those differences seem to be primarily focused on the basic electrical components on the board. The various writings on the 2nd generation Gigabyte P965 boards (i.e. AnandTech 01/26/07) seems to strongly suggest that stability over a wider range of voltage and speed settings was a serious focus of these revised boards. It wouldn't surprise me a bit to learn that all of this revision work was at least partially intended to ensure a socket-compatible board that would accept these new 45nm processors


RE: New arrival
By SunAngel on 1/27/07, Rating: 0
Will Nehalem use Socket 775?
By Josh7289 on 1/27/2007 2:48:02 PM , Rating: 2
Will Nehalem use Socket 775 like Penryn or will it be an entirely new socket?




RE: Will Nehalem use Socket 775?
By Viditor on 1/28/2007 10:45:07 PM , Rating: 1
quote:
Will Nehalem use Socket 775 like Penryn or will it be an entirely new socket?

It's still not known, but I would bet everything that it will be a new socket as it's for a whole new platform.


RE: Will Nehalem use Socket 775?
By JackPack on 1/29/2007 3:39:36 PM , Rating: 2
New socket for sure - 1366? CSI ain't coming for free.


By Crazyeyeskillah on 1/27/2007 12:55:55 AM , Rating: 2
Good time to pick up the sails and PR the hell out of AMD's chance to crawl back into the market. I don't think The Exec's at Intel were so excited about the market share they saw slip away the years prior to core2duo. . .It is unlikely that we will see AMD gain that type of distance again despite better distribution and partnerships in the industry. Good to see Intel taking the initiative to drive their capabilities into new breakthroughs for consumers. Good product + Good price = Happy, repeat consumer.




Add some spice to article.
By crystal clear on 1/27/2007 10:06:44 PM , Rating: 2
Some production news-

The first commercial Penryns will come out of Intel's D1D and Fab 32 facilities in, respectively, Oregon and Arizona. A third plant, Fab 28 in Isreal, will come on stream in H1 2008. All three are 300mm-wafer fabs.

The 45nm Core 2 Duo, Core 2 Extreme, Core 2 Quad and Xeon processors Intel will build out of Penryn will match today's chips' power envelopes - 35W for laptop chips, 65W for mainstream desktop parts, and 80W for quad-core server and the gaming-oriented CPUs - Intel said, with the benefits of the shift in scale from 65nm to 45nm delivering higher performance.

http://www.reghardware.co.uk/2007/01/27/intel_reve...




Underwhelming...
By ybee on 1/27/07, Rating: 0
This is pretty funny
By Beenthere on 1/27/07, Rating: -1
RE: This is pretty funny
By Warren21 on 1/27/2007 11:12:55 AM , Rating: 2
Don't believe everything you read in the tabloids, kid. I'd take that 40% with a grain of salt.

Secondly, the high-k stuff is in AMD's 65 nano products, not 90.

Also Intel's lact-luster performance for the past two years has nothing to do with process technology, it's architectures. K8 is why AMD crushed Intel P4/Xeon performance in the past.

Don't look at Intel's process advancement (they are several months ahead of AMD on shrinks, I mean 6 months+ -- it's always been atleast that big of a gap) as a cheap hack to get past AMD -- look at Intel's 65 nano P4's and Pent D's, they still suck just as bad as the 90 nano versions -- it's their superiority in being several months ahead on their process shrinks.


RE: This is pretty funny
By Warren21 on 1/27/2007 11:14:22 AM , Rating: 2
Edit: Meant 45nm for AMD's high-k, not 65.


RE: This is pretty funny
By ScythedBlade on 1/27/2007 3:35:17 PM , Rating: 3
Try more like a year instead of several months ..


RE: This is pretty funny
By ChipDude on 1/27/2007 11:45:02 PM , Rating: 2
Hi K is absolutly NOT in AMD's 65nm. AMD is using the same old boring nitrided oxide they used in previous generations.

AMD/IBM have already stated they are NOT using HiK in their 65nm. All they could do was lower the K a bit for the backend and throw immersion in because they couldn't figure out how to pattern with 193nm dry.


RE: This is pretty funny
By flipsu5 on 1/28/2007 2:34:17 AM , Rating: 2
Immersion is only in their 45 nm. It's the other way around. Intel is not doing immersion because they do not have the tools in time for ramp.

Both AMD and Intel were prepared to do 45 nm with or without high-k.

The only barrier to doing BOTH immersion and high-k is purely cost of two dramatic changes at once, since you would need new hardware for both processes.


RE: This is pretty funny
By Viditor on 1/30/2007 3:40:21 AM , Rating: 1
Remember also that there is a difference between the 2 HK/MG processes here...
Unlike Intel, IBM has figured out how to embed its new metal gates directly into silicon (Intel's gates must still sit atop a silicon architecture structure).
This will be even more important as they shrink to 32nm and 22nm...


RE: This is pretty funny
By ChipDude on 1/30/2007 11:19:58 AM , Rating: 2
Another brilliant technologist.

Tell me if you embed the gate in the silicon how it acts like a gate. Do you know what MOS transistor stands for?

Metal on Oxide on Silicon = MOS

Now INTEL has put real metal on top of an Oxide ( HiK ) on silicon to form a MOS transistor.

Putting Metal in the silicon causes nasty things, degraded lifetime, high junction leakage etc. etc.


RE: This is pretty funny
By Viditor on 1/30/2007 7:32:06 PM , Rating: 2
Another EE student who's forgotten how to read articles...

http://www.techworld.com/opsys/news/index.cfm?news...

Intel's manufacturing lead should allow it to bring chips to market before its rivals, but IBM could get a greater return from this technology in the long term because it uses the high-k metal gates in a different way, one analyst said. "It's a wonderfully parallel development of a technology that should lead to faster, more efficient chips in everything from PCs to cell phones and iPods," said Richard Doherty, senior analyst with The Envisioneering Group.

"Intel has the advantage that they're already in production, but IBM's advance may be even more significant and lead to faster, smaller chips. The IBM breakthrough is to integrate the metal gate so it's embedded in the silicon. Intel put the metal gates on top of a proven silicon architecture."


RE: This is pretty funny
By Khato on 1/30/2007 8:12:27 PM , Rating: 2
quote:
AMD plans to produce its first 45nm chips in mid-2008, in the wake of the launch of its first 65nm product, the quadcore "Barcelona", due out in mid-2007.


Reading some articles is indeed rather humorous. Anyway, quotes from analysts don't tend to mean much to me. Far more interesting is to look at the IBM research paper on the matter that the register posted up: http://regmedia.co.uk/2007/01/28/ibmhighk.pdf

Their 'embedded in the silicon' is actually a conventional poly-Si deposited over the metal gate, something that really -should- be quite unnecessary. Anyway, what I love about the paper is the info on their HK/MG pFET devices, the fact that their test SRAM array was using conventional SiON/Poly-Si pFETs says something about how 'ready' their high-k process is.


RE: This is pretty funny
By Viditor on 1/30/2007 8:54:34 PM , Rating: 2
quote:
quotes from analysts don't tend to mean much to me

Fair enough...and thanks for the link!
quote:
the fact that their test SRAM array was using conventional SiON/Poly-Si pFETs says something about how 'ready' their high-k process is

I believe that East Fishkill has already been converted to HK/MG...the key is that the IBM conversion appear to be a much simpler process...

"We don't build Vespa scooters, we build Ferraris. We've been talking about high-k for five years now, and if we wanted to, we could ship it out the door tomorrow. But there's no reason to do that because it doesn't solve any problem for us. We're not addressing a crisis issue that hit us in the head when we didn't see it coming," Meyerson said.

"Ours is a more fundamental implementation; it's a drop-in, or a one-for-one replacement, for SiO2 ," he said, referring to existing silicon dioxide technology. "I've said for years that gate oxide scaling is ending. The gates are literally five atoms thick. What are you going to do, build one that's two-and-a-half atoms thick?"


The interesting questions for me are
1. What is Intel's goal/need for HK/MG? (meaning from a marketing or performance standpoint)
2. How will ultra-low k connects compare to Intel's process and what will that mean for marketing/performance?


RE: This is pretty funny
By Khato on 1/31/2007 1:41:50 AM , Rating: 2
Yay, yes, the quote from the engineer was the highlight of that little article =D Granted, he has the typical bias towards his company, but, don't we all? Anyway, my little comment on the bolded portion is that it can't be a one for one replacement of SiO2 with HfO2, since there are problems with using Poly-Silicon directly on the halfnium oxide (it'll work, but not near so well as with metal gate.) But, eh, they don't get into enough detail to say how it's 'drop in'.

1. I would assume it's more a marketing point - performance per watt. True, the average consumer doesn't care as much about it. But system integrators love it for easing the cost of cooling designs. And it has fast become -the- metric in many server applications. So what if server X outperforms server Y by a small amount if two X's consume the same amount of energy as one Y?

2. That is indeed an interesting query. Heh, at the current dimensions interconnects are getting to be far more of a factor, no question. Still, on Intel's 45nm info page, they have the interesting little statement of, "Approximately 30 percent reduction in transistor-switching power." This is indeed a tad bit vague, if in comparison to 65nm, the majority could be due to voltage decrease. But, the remaining amount would be due to reduced capacitances, and I would guess that amount is at least as much as what the ultra low-k interconnect dielectrics would offer.


RE: This is pretty funny
By Viditor on 1/31/2007 7:24:38 AM , Rating: 2
quote:
they don't get into enough detail to say how it's 'drop in'


This is well over my head, but the link you provided says:

Short channel HK/MG devices were fabricated from <20Å HfO2 with
thermally stable BE metal gates in a gate-first approach where
conventional poly-Si is deposited over the metal gates. Following a
lithographic patterning and gate stack etch process, a conventional selfaligned
implant process flow with a final S/D spike RTA (T>1080°C) +
advanced annealing (AA) and dual stress liner (DSL) with conventional
MOL and BEOL was used


Does that help? :)



RE: This is pretty funny
By Khato on 1/31/2007 11:39:38 AM , Rating: 2
I'll freely admit that I shied away from the 8000 level semiconductor properties course after having gotten through the 5000 level one, so I don't understand quite everything either, lol.

What I find mildly confusing about all the stuff IBM has said is that they're being rather mute on a change to metal gate electrodes. Technically, they'd have a high-k metal gate by simply using hafnium as the gate dielectric and continuing to use poly-Si for the gate electrode. (After all, hafnium is a transition metal.) I'd hope it's simply the press releases dumbing it down that make it seem as such. But the fact that the paper lacks any mention of a metal gate electrode and -does- say that poly-Si is deposited over the metal gates is a tad bit worrysome. Maybe they'll have further information in time, just seems odd that they're not mentioning anything about the gate electrodes really.


RE: This is pretty funny
By flipsu5 on 2/6/2007 11:30:27 PM , Rating: 2
Some more details are reported in another paper at the 2004 VLSI symposium on VLSI Technology "Thermally robust dual-work function ALD-MNx MOSFETs using conventional CMOS process flow".

The metal gate (TaN for N, WN for P) is thin (~10 nm) and deposited by ALD. The polysilicon is needed to be on top to enhance the thermal stability. I also know it shields the gate dielectric better from lithography radiation; the metal is too thin.


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