quote: have been a AMD fan for years, since they give better bang for your buck.
quote: I wonder what's AMD's response to this?
quote: Do you feel pretty confident about AMD's response (OK, riding on IBM's coat tails) to this breakthrough advance in lithography?
quote: It seems you were pretty confident back about a year ago and it did not quite pan out..
quote: SUN a long time partner of AMD switches over to INTEL
quote: Then you will notice AMD is slowly to be put aside- A downgraded relationship
quote: One curiosity in that press release, nothing is mentioned about the previously touted low-k interconnect dielectrics and immersion lithography
quote: There shouldn't be any problem combining the two different dielectrics seeing as how they'd have limited contact points
quote: If IBM had anything to annouce they would have annouced in December at IEDM
quote: Sad fact is they have one fab making game chips and CPUs to the tune of 20-50 million units
quote: You mean like Intel's announcement...no, wait.
quote: So now Intel needs to tout it's prior technological achievements at every conference in order to keep in the lead?
quote: Silly silly silly, have you taken an undergraduate device physics course and understand KT/Q? Vt can't be lowered anymore at room temperature without excessive leakage as you will lower the barrier between source and drain. Anything much lower then 400mV and you can't turn the transistors off. Thus you can't just reduced the drain voltage as Vdd-Vt won't be enough to dry that lowK backend.
Thus to get good drive current and minimum leakage you need Vdd about 1 volt or so. Any lower and you get really low performing transistors. Of course in sleep/slow mode you can do all you want reduce Vdd but then you have this thing called SRAM stability to deal with.
High K / Metal gate is as close to having your cake and eating it to!
quote: SiO2 buffer layer, really? Think thru what you said. Today we can't support a thinner electrical thickness and control leakage. Now you tell me you need a layer of Oxide then add some thicker HiK and get a thinner electrical oxide then a nitrided oxide... Sorry is that HiK have negative effecitive oxide thickness? If you add a buffer of oxide then you negate all the benifits of having HiK helping your eletrical TOX.
quote: Extended halt power for core 2 duo is 22/12W (available in Intel's datasheet.) Believe the 12W figure is for the 2MB. Either way, yes, gate leakage can be more of an issue when not in standby, depends upon the design.
Anyway, all those figures are based upon the current conroe at 3GHz. And even if you increase the figure by the amount of core logic increase going into wolfdale, you still only get 50W. Either way, at this point it's all just speculation anyway. Intel's current figures are just based on simulations since silicon isn't at speed. So even if that was an actual roadmap, Intel wouldn't have lowered TDP on it in the least.
quote: I'm not involved in the process engineering, so I don't know exactly what method Intel's high-k process is using. Seeing as how it's a trade secret, I doubt anyone who does would post it. That said, what does the interface between dielectric and silicon have to do with electron mobility through the channel area? Part of the desirability of halfnium in my understanding was that it interfaced so nicely with silicon, the problem was always on the gate electrode.
quote: Penryn still consumes same power as Merom
quote: I'm certain that's why there was this lovely little slide from IDF that stated CPU TDP in 1H'07 would be 1/2 of the value in '06, while in '08 it would be approximately 1/10 of the '06 value.
quote: I no need to comment much on the validity of the link provided, seeing as how it says right in the link 'editorial' and it's a subscription required site. I far prefer scouring around for information from the source, it's not that difficult to do.
quote: the window of opportunity for AMD has probably closed and their implementation of it isn't likely to occur until 32nm
quote: Core2 architecture is natively dual core
quote: HyperThreading was primarily possible on the Pentium 4s due to the ulta long pipeline.
quote: Penryn will launch on Socket 775, meaning existing motherboards can physically harbor the new CPU, but electrically might not.
quote: However, the Smith also claimed the Penryn boot test that grabbed so many headlines last week occurred on unmodified hardware that included a notebook, several desktop motherboards and several server motherboards.
quote: Will Nehalem use Socket 775 like Penryn or will it be an entirely new socket?
quote: AMD plans to produce its first 45nm chips in mid-2008, in the wake of the launch of its first 65nm product, the quadcore "Barcelona", due out in mid-2007.
quote: quotes from analysts don't tend to mean much to me
quote: the fact that their test SRAM array was using conventional SiON/Poly-Si pFETs says something about how 'ready' their high-k process is
quote: they don't get into enough detail to say how it's 'drop in'