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Hardware JEDEC Finalizes DDR3 Specifications
Anh Tuan Huynh (Blog) - June 27, 2007 4:33 PM
Print E-mail del.icio.us 13 comment(s) - last by y2ktan.. on Jul 9 at 3:07 AM

Kingston DDR3 and DDR2 DIMMs compared
DDR3 specification finalized after memory and motherboards ship

JEDEC today finalized and published the DDR3 memory standard (DOC). The DDR3 memory standard promises dramatic improvements that deliver greater performance while consuming less power than DDR1 and DDR2. DDR3 memory drops voltage requirements down to 1.5-volts from DDR2’s 1.8-volt requirement and DDR1’s 2.5-volt requirement. Memory manufacturers can increase voltage to achieve greater speeds, as with high-end overclocking memory.

“The DDR3 standard will serve as the lynchpin for developing a new generation of memory solutions that address demands for both lower power and high performance,” Intel Director of Platform Memory Options and JEDEC board member Paul Fahey said. “DDR3 will be an essential ingredient in future mobility platforms and those applications requiring the highest performance, such as video-on-demand, encoding and decoding, gaming and 3D visualization.”

JEDEC also touts increased operating temperature range, memory device reset, burst chop, dynamic on-die termination, output driver calibration and write leveling as new features of DDR3 memory. The new features allow DDR3 memory to scale to higher speeds while retaining the module form factor. With the DDR3 standard, memory manufactures can offer chips in 512Mbit to 8Gbit densities in either monolithic or stacked packaging.

“The DDR3 standard represents the culmination of countless hours of collaboration between memory device, system, component and module producers,” JEDEC JC-42.3 Chairman and AMD employee Joe Macri said. “This standard will permit emerging systems to achieve greater performance, storage and functionality, consistent with the needs of an increasingly information-intensive world community.”

DDR3 memory modules for desktops have 240-pins, just like DDR2. However, DDR3 and DDR2 memory modules and slots have notches in different places. The physical differences in memory modules prevent users from accidentally installing DDR2 modules into DDR3 slots and vice versa. JEDEC has also published specifications for DDR3 SODIMM modules for mobile and limited space uses. As with DDR2 and DDR1 memory, JEDEC has published specifications for registered and unbuffered DDR3 modules.

DDR3 platform support is limited to Intel Bearlake-family chipsets. Intel expects DDR3 to become mainstream next year with the release of the Eaglelake chipset family. AMD plans to join in with DDR3 support with Socket AM3 processors in 2008.

Expect DDR3 memory modules from the usual manufacturers such as Corsair, G.Skill, Kingston, OCZ Technology, Super Talent and others.

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8GB DIMMs?
By dolcraith on 6/27/2007 9:21:42 PM , Rating: 2
So that's a possibility of a 8Gbit chip,with 8 chips per dimm would result in a 8GB module? (8x8192)

Correct me if I'm wrong, but theoretically you could get a 36GB of ram with 4 slots. (Assuming the memory controller can handle the ram)




RE: 8GB DIMMs?
By MasterTactician on 6/27/2007 10:53:33 PM , Rating: 5
Yes, you are worng. It would be 32GB (8x4), not 36. lol.


RE: 8GB DIMMs?
By Egglick on 6/28/2007 2:34:04 AM , Rating: 2
Manufacturers typically use up to 8 chips on each side of a DIMM. This means you could theoretically have a 16GB module of DDR3.

We'll probably be several new memory standards down the line before such densities are necessary though.


RE: 8GB DIMMs?
By defter on 6/28/2007 3:26:59 AM , Rating: 2
Server memories use often stacked chips, which means there can be 36 chips on a DIMM giving 32GB DIMMs (with ECC) :)


RE: 8GB DIMMs?
By oTAL (blog) on 6/29/2007 5:59:54 AM , Rating: 2
4 X 8 = 36....

Hmmm... State sponsored math degree? ;)


"Write-leveling"?
By darkfoon on 6/27/2007 5:55:23 PM , Rating: 2
Why would regular DRAM need write leveling? Its not like DDR3 is some sort of flash memory.

The reason I can see for write-leveling is to help lessen the "memory effect" that occurs in DRAM when data is stored in the same location for any period of time.




RE: "Write-leveling"?
By TomZ on 6/27/2007 6:01:23 PM , Rating: 5
quote:
Why would regular DRAM need write leveling?

For improved signaling, DDR3 modules have adopted fly-by technology for the commands, addresses, control signals, and clocks. Due to signal routing, this technology has an inherent timing skew between the clock and DQ bus at the DRAM. Write leveling is a way for the system controller to de-skew the DQ strobe (DQS) to clock relationship at the DRAM. A simple feedback feature provided by the DRAM allows the controller to detect the amount of skew and adjust accordingly.
http://www.micron.com/support/designsupport/faq/dd...


By PAPutzback on 6/28/2007 8:12:36 AM , Rating: 4
Can't they make 2 gig so-dimm sticks that are as fast as full length ones. It just seems to me that the smaller we make everything the better it is in the long run. How about instead of 4 banks of dimms we have 8 of so-dimm.




great
By Gul Westfale on 6/28/2007 2:04:34 AM , Rating: 3
it's nice to see that rather than the obligatory throughput and lower voltage we also get more features. i must admit i don't know what all of them are but it's nice to see this. i was disappointed with DDR2 because of the high latency, but maybe DDR3 will be better.




DRAM Error Checking
By y2ktan on 7/9/2007 3:07:51 AM , Rating: 2
Does anyone know how the DRAM perform the ECC checking and how the 8-bits of check bits are generated by DRAM ? I cannot find any information regarding the error checking for DRAM in JEDEC document. Does anyone have the information?

Thanks in advance.




1st
By ButterFlyEffect78 on 6/27/07, Rating: -1
RE: 1st
By Scabies on 6/27/07, Rating: -1
RE: 1st
By shabby on 6/27/2007 8:19:12 PM , Rating: 5
Too bad you cant rate it to a point where it'll be deleted :)


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