After a year of delays due to process problems, Broadwell finally prepares for a broader release; but did it break Moore's Law?

Intel Corp.'s (INTC) first widely available chips built on its new 14 nanometer (nm) scale node are finally here.  The new shrunk core design is code-named Broadwell.  And while Broadwell promises big gains, it's a year late in practice, if not in principle.  And that raises some tough questions for Intel.

I. Llama Trail and the Story of the Missing 5th Gen. Core i-Series

Intel had originally promised 14 nm chips to arrive in Q4 2013.  This target slipped due to serious defects at the 14 nm node, and Q1 2014 became the new launch window.  This slipped again to H2 2014, nearly missed the pivotal back-to-school shopping season.

Llama Trail
The first Broadwell chips shipped in limited quantities as Llama Trail convertible CPUs.
[Image Source: Aiam Nut/Lauren Prinzo/Pinterest]

After soft launching in June 2014, Intel finally debutted the first actual real-world Broadwell devices in September.  All of these were based on the convertible-targeted Llama Mountain (2-in-1) Core M chips.  The first Llama Mountain device to ship was the refreshed ThinkPad Helix from the Lenovo Group Ltd. (HKG:0992).

The refreshed version of Lenovo's ThinkPad Helix convertible 2-in-1 tablet/laptop PC was among the small stock of convertibles to ship in the fall with Broadwell Core M chips inside.

A handful of other Llama Mountain devices would follow:
  • Lenovo Yoga Pro 3 (Oct. 2014)
  • Acer Inc. (TPE:2353) Aspire Switch 12 (Sept. 2014)
  • Hewlett-Packard Comp. (HPQ) Envy X2 (13.3-in. and 15.6-in. models) (Sept. 2014)
  • Dell Inc. Latitude 13 7000 (Sept. 2014)
  • ASUSTek Computer, Inc. (TPE:2357) UX305 Zenbook (Sept. 2014)
The convertibles were driven by a handful of Core M chips.  All came with:
  • CPU -- Broadwell
    • 2x cores
    • 4x threads
    • 4 MB L3 Cache
  • GPU -- HD 5300 (GT2)
    • on-die graphics processsing unit (dGPU)
    • 24 shader cores
    • @ 100 MHz (base) w/ turbo upclocking
  • Power
    • cTDP (down): 3.5 W
    • Nominal: 4.5 W
    • cTDP (up): 6 W
At total of seven chips were release in the Core M/Llama Trail family -- three in Sept. 2014 and then another four in Oct. 2014.

Intel Core M

But the key factor is that none of these devices were very hot sellers (no Windows 8.1 convertible was, for that matter).  

The naysayers were wrong about Intel's Broadwell missing 2015 -- sort of. Intel did release something at 14 nm, albeit at mass volume.  That said, they were also sort of right.  The mass market chips -- the Celerons, Pentiums, Core i3s, Core i5s, and Core i7s were still stuck on Haswell -- until now.

The Verge's Vlad Savov aptly summarizes, "Frankly, even the already announced Core M devices haven't shipped out in massive volumes, so Broadwell's day zero is really and truly today."

II. Broadwell-Based Core i-Series: Better Late Than Never

On Monday Intel effectively opened the floodgates, at last announcing a full 5th generation Core i-Series family based on Broadwell.  In total Intel announced 17 new Broadwell chips -- two Celerons, a Pentium, three Core i3, six Core i5s, and five Core i7s.

Here's the chips:
Intel Broadwell

Note all the chips announced are dual-core designs.  That's right; there's still no quad-core, hexa-core, or octa-core Broadwell based designs.

Intel is perhaps taking a book from Apple, Inc.'s (AAPL) iPhone/iPad SoC design, recognizing that releasing a chip with a lesser complement of well-designed cores can trump a larger ensemble of cruder cores.  But likely Intel will eventually flesh out its lineup with quad-core and higher stock, once it irons out the remaining process issues.
Intel Iris 6100 and Broadwell

Intel Broadwell Improvements
Intel's own press release made it pretty clear that this was the first widespread availability of Broadwell chips.  It wrote:

Today, Intel unveiled the 5th Generation Intel® Core™ processor family. Built on Intel’s cutting edge 14nm manufacturing process, the 5th Gen Intel Core processors deliver premium performance, stunning visuals and enables improved battery life to take computing to the next level. The performance also provides the foundation for more natural and interactive experiences with Intel® RealSense™ technology, Intel® Wireless Display (Intel® WiDi) and voice assistants. With the “Broadwell” microarchitecture expected to be the fastest mobile transition in company history, offering consumers a broad selection and availability of devices, the 5th Gen Intel Core processors are purpose-built for the next generation of compute devices offering a thin, light and more efficient experience across traditional notebooks, 2 in 1s, Ultrabook™ devices, Chromebooks, All-In-One desktop PCs and mini PCs.

Overall the new Broadwell SoCs pack roughly 1.9 billion transistors -- up around 50 percent from the 1.3 billion Haswell had.  The die size, meanwhile, shrunk from 181 mm2 with Haswell to 133 mm2 with Broadwell.  Thus the overall density jumped from around 7.2 million transistors per mm2 of die space to 14.3 million transistors per mm2 of die space, a trend that's in keeping with the traditional doubling of circuit density every two years.
Broadwell die
Broadwell is limited to dual-core designs at present.  An on-die GPU w/ 12 execution units is seen at the bottom, indicating this is a Core M chip or a Pentium/Celeron Core i-Series design.

Graphics on the device are Intel eight generation integrated graphics (IGPU).  They're laid out in "slices" -- chunks of 24 shaders and independent shared L3 access. A slice is relatively similar component-wise to NVIDIA Corp.'s (NVDA) streaming multiprocessing (SM) units.

Intel Broadwell

The new Broadwell chip packs a new platform controller hub (PCH), a secondary chip on the package with the main SoC.  It still provides recent improvements like vPro support, basic I/O (SATA, etc.), and high-speed PCI-E storage support.  

Intel Broadwell PCH

It's now interesting audio (and microphone processing) I/O abilities and thermal/power management to its list of duties.  The latter addition adds roughly an hour and a half of battery life during video playback, according to Intel.

III. Wireless-AC 7260, Cherry Trail, and XMM 726X LTE-A Modem

Also announced was a new companion Wi-Fi chip, the Intel Wireless-AC 7265.  The successor to the Wireless-AC 7260, the new chip comes with a new ball grid array (BGA) form factor dubbed 1216, which stands for its size -- 12 x 16 mm.  It boasts improvements to peak throughput and power performance both in the idle and active states. 

Intel Wireless AC 7265

Intel also announced that it was "shipping" Cherry Trail; 14 nm tablet Atom processors.  Cherry Trail is the die shrink of the 22 nm Bay Trail tablet chip line, a chipset that saw modest consumer success.  Cherry Trail comes with an LTE-A companion modem, the XMM 726X.  Intel didn't share specific model details of the tablet chips.

Cherry Trail
Intel thinks Cherry Trail will bear fruit in the tablet space. [Image Source: FreeHDW]

About all it did say was that the chips would pack support for RealSense, a depth-sensing technology, which combined with a user-facing camera can be used to increase the speed and security of faster facial recognition logins.  It can also be used in more novel scenarios to determine the user's emotions (based on facial expression).

Cherry Trail

Intel says Cherry Trail chips will ship in "H1 2015".  There's no word yet on when their smartphone companion chips will join them, but expect those to drop in H2 2015 at the earliest, or possibly even not land until H1 2016.  Cherry Trail chips will be succeeded by Broxton designs later next year.  A new modem design called SoFIA is also expected to debut in 3G and LTE form.  It will be available directly integrated into Cherry Trail chips, similar to Qualcomm's on-die LTE-A modems.

IV. But Wait, Didn't Intel Break Moore's Law?

Intel's somewhat overdue release of Broadwell brings some tough questions.  The biggest of them is whether Intel broke from "Moore's Law" -- the trend observed by its cofounder Gordon E. Moore in his famous 1965 paper discussing transistor size trends.  Moore's law states that the # of transistors in a dense circuit doubles every two years.  Intel has taken to introducing a die shrink (traditionally) every two years -- the so-called "tick".

Intel Moore's Law

People have long been predicting the "death of Moore's Law" and, happily, Intel and others have long been proving them wrong.  In recent years even as Intel's rivals struggled, Intel has been remarkably steady with its die shrinks -- regular as clockwork, you could say.

The last two die shrinks (22 nm and 14 nm) haven't been quite as timely, though.  Westmere (the 32 nm die shrink of Nehalem) shipped in Q1 2010.  The first 22 nm Ivy Bridge chips hit the market in Q2 2012.  And the Core M line debuted in Q3 2014.  So if we take Intel's launch dates for the past two die shrinks, Intel is requiring one extra quarter per cycle to squeeze out the next die shrink  -- 2 and 1/4 years.  That's not really the major concern.

The more serious concern is that on the other hand, if you take Q1 2015 to be the "true" release date of Broadwell, a more alarming picture emerges.  In that scenario Ivy Bridge slipped by one quarter, and Broadwell slipped by three quarters due to process issues (i.e. Broadwell's die shrink took 2 and 3/4 years, the argument would go).  Now you have a trend of increasing slippage.

So is Intel slipping and fall off of the old trusty Moore's Law?  Tupac Shakur once told his critics in a rap lyric, "Only G-d can judge me."

Sadly for Intel, it won't just be a higher power that's judging.  The market -- and analysts -- have and will surely judge Broadwell (based in part on its somewhat tardy Core i-Series arrival).  My personal feeling, though, is that we should reserve judgement on Intel's "slippage" or lack thereof until Cannonlake, the 10 nm die-shrink fo the upcoming the new Skylake microarchitecture.

Intel die shrink
The 10 nm node will give a clearer picture of whether Intel's process cycle (and Moore's Law) is slipping.
[Image Source: Jason Mick/DailyTech]

Let's for a second assume the naysayer's scenario that Intel slipped this generation.  Whether that's a sign of bigger trouble can be most fairly assessed, I would argue, by when the Core i-Series 10 nm Cannonlake chips land.

If they land:
  • Q3 2016, then Intel is in great shape having made up for lost time. (the "best" case)
  • Q4 2016, then Intel required 9 quarters for the die shrink, same as the last generation, but the 12 quarter dev. cycle of the Broadwell shrink was just a hiccup. (the "okay" case)
  • Q1-Q3 2017, then Intel's dev. cycle for die shrinks has elongated to around 2 and 1/2 or more years, but slippage is not increasing, at least. (the 'bad, but not terrible" case)
  • Q4 2017 or later, then Intel is not only seeing a departure from Moore's Law, but it's getting worse. (the "worst" case)
The trend from Ivy Bridge and Broadwell would tempt one to believe that the latter ("worst" case) scenario is the most likely one.  But it's really kind of hard to tell whether Intel's delays are a one-off issue or a sign of something far worse.

V. Understanding the FinFET and What Changed

On a deeper level you may wonder why Broadwell took so long, how we got here, and how 14 nm stacks up versus 22 nm on a transistor level.

The story begins more than ten years ago at Intel, but picks up in earnest several years back.  Work on Broadwell began last decade in the labs at Intel and by 2011 Intel was prepping fabs for 14 nm production.

Most of the world's other best chip fabs -- including Samsung Electronics Comp., Ltd.'s (KRX:005930) (KRX:005935) and Taiwan Semiconductor Manufacturing Comp., Ltd.'s (TPE:2330) (TSMC) -- are only just now reaching volume production of logic chips at 20 nm.

This is notable as it shows that Intel not only is ahead in feature size, it's also followed a more aggressive development path, shrinking from 32 nm to 22 nm (a 31% linear feature size reduction) to 14 nm (a 36% feature size reduction).  By contrast, rivals have gone from 32 nm to 28 nm (a 12% feature size reduction) to 20 nm (a 29% feature size reduction).

Intel is able to sculpt the tiny features with complex multi-patterned forms of immersion lithography (it hopes to stick with this process through the 11 nm node).  To understand this, we must first recall how the FinFET works.

In a traditional field effect transistor, a voltage is applied to gate, which lies over a doped layer of silicon between the source and drain, called "the channel".  The voltage changes the electrical characteristics of the channel, allowing electrons to flow from the source to the drain, switching the transistor on.  The important thing to note is that the gate is a trench under a 2D plane.

FinFet making
FinFETs require the growth of multiple 3D channels ("fins") embedded in the gate. [Image Source: synopsys]

The channel is now 3 dimensional.

In a FinFET, the channel is embedded up into the gate in a fin.  The gate exerts a voltage on the doped silicon on all sides, effectively creating a thin 3D dimensional channel, with the majority of the channel being in vertical planes.  In traditional planar transistors, the node size was dictated solely by the gate length (or width, if you will) across the exposed channel.  So a 32 nm transistor was called thus because its channel (and gate width) were 32 nm wide.

In FinFETs the same convention was kept, but remember that now you have an extra variable -- the fin.  So die shrinks commonly involved modifications to the geometry not just in a linear scale, but in a complex three dimensional dance.

VI. Those Tricky Fins

One of the trickiest parts of the die shrink to 14 nanometers was perfecting the trigate fins -- the feature that gives the transistor its "FinFET" (fin field effect transistor) nickname.  

Unstrained silicon has a lattice constant of 543 picometers (pm).  The lattice constant tells you the distance between surface atoms.  The fin for the 22 nm node was roughly 12 nm across at its base -- or roughly 22 atoms across.  At the 14 nm node, the fin is 8 nm thick at its wides, indicating that it is a mere 14 atoms across at its widest.  At the tip, for 22 nm, electron micrographs show a tip that appears a mere 5-6 atoms wide (see Chipworks, analysis, for example).  Unsurprisingly the 14 nm fin was made a bit more rectangular, as getting tapers to 3-4 atoms would be daunting.

That may have been part of what forced Intel to spend so long tweaking the design (plasma damage to the low-K materials is another likely culprit).  Ultimately Intel arrived at a fin that's 50 percent thinner at the bottom, but just barely thinner at the top.  The triangular taper is retained, but the fin creeps closer to being rectangular (see images below).

Senior Intel Fellow Mark T. Bohr remarks:

To meet the challenges of the 14 nm process, trigate fins were once again the area of focus.  We made them taller, thinner, and spaced closer together.  This improved technology provides three major benefits.  First of all it is faster, allowing more processing and ultimately better performance.  Secondly, the new design requires less active power contributing to better battery life and also helping to reduce our carbon footprint.  Third, the new 14 nm fins are so effective that we can get away with fewer of them, requiring even less area per transistor.

So versus the 22 nm design, the third fin is dropped.  The channel shrinks from around 12 nm across at the 22 nm node to 8 nm at the 14 nm node. And the height of the doped fin channel raises from 34 nm to 42 nm, increasing the channel surface area in the vertical direction.

That allows the fins to be brought closer together, shrinking from 60 nm apart, to a mere 42 nm apart.  Similarly, interconnects (80 --> 52 nm) and transistor gates (90 --> 70 nm) decrease in pitch density.  These changes are summarized in the following slides.

Intel Broadwell FinFET

Overall, these gains extend the density gains past mere single-dimensional shrinking of the channel length.  At the same time, by extending the transistor higher up, Intel has used their third dimension -- height -- to mitigate the adverse effects (leakage, etc.) of this compaction.  It has also tapped exotic materials like high-K and low-K dielectrics to improve performance at the tiny gates.

But all that appears to have taken Intel a long time to get right -- particularly the 3D manufacturing side of things, if varability in fin width/tapering at the 22 nm node was any indication.

VII. What's Next

Looking ahead, the die shrink road for Intel is only going to get tougher.  For 10 nm, Intel expects to need to employ a quintuple (5x) masking scheme.  To reach the next two nodes -- the 5 and 7 nm nodes -- Intel will have to deploy a brand new form of lithography, extreme ultraviolet lithography (also known as "deep violet" lithography).

extreme ultraviolet lithography

To reach 7 nm and below, Intel will likely need to turn on extreme ultraviolet (EUV) lithography.
[Image Source: SEMATECH/]

The hope is to keep on shrinking to 1 nm by sometime around 2030.  But if the difficulties Intel ran into at 14 nm are any expectations, it could easily be 2040 or even 2050 before the limits of silicon lithography (~1 nm feature size) are reached.  Intel will likely then be forced to turn to novel transistor materials like switchable phosphorousmolybdenitemetallic nanocrystalsgraphene, fullerene, quantum dots, and/or carbon nanotubes to extend things to an even tinier atomic scale.

Graphene sheet
Intel and others will likely turn to exotic transistor materials, such as graphene (carbon-based planar polymers) in the post-1 nanometer era. [Image Source: io9]

The good news is that these challenges are universal, affecting not just Intel, but its rivals as well.  If anything, Intel is the best suited to deal with them.  But that also doesn't change the underlying fact that Intel's business model of selling yearly upgrades is in jeopardy, unless it can figure out a way to continue to aggressively advance the modern circuit in the post-lithography era.

But in order to keep its profits up, it will have to turn to new kinds of technology like 3D circuits and small "internet of things" (IoT) processors in order to keep luring in buyers each year, as the pace of die shrinks inevitably slows.


IoT @ IDF 2013
Intel talks "internet of things" (IoT) at IDF 2013. [Image Source: Jason Mick/DailyTech LLC]

One major variable outside Intel's control is what rival third party fabricators will manage to do. Both Samsung and TSMC are pursuing FinFETs in the 14 to 18 nm range.  It remains to be seen exactly how these stack up to Intel geometry-wise (reports indicate, for example, that Samsung is targeting a more rectangular cap to its fin gate geometry, perhaps broadening the channel width).

Some reports indicate Samsung may be producing the Apple A9 on a special contract at 14 nm.  That chip could debut as early as this year.  If the rumors prove true, it would indicate Samsung is only 2-3 quarters behind Intel.  Other signs indicate that may not be the case.

Samsung -- catchup

Samsung hopes to catch up to Intel debuting 14 nm production later this year.
[Image Source: Samsung Electronics]

It should be interesting to watch the battle unfold at the end of the road for immersion lithography between Intel and its rival chipmakers.  It should also be interesting to see if any of them -- Intel included -- can maintain a pace remotely close to Moore's Law in the EUV patterning era and beyond.

Sources: Intel [press release], [fact sheet; PDF]

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