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Intel's Paul Otellini holding up a 32nm test shuttle with SRAM lithography
The company is on track to bring its 32nm process in 2009

Intel today showed off its first test shuttle manufactured on a 32nm node process. Intel CEO Paul Otellini showed off the working 32nm chips during his keynote at the Intel Developer Forum. Although the test shuttles are working samples, the 32nm wafer contains no logic and just a test run of 32nm process technologies. Intel test shuttles are typically just SRAM.

The company plans to begin production of 32nm process processors in 2009 with the refresh of Nehalem Westmere. Westmere’s 32nm die shrink follows Intel’s tick-tock strategy, which alternates between process shrinks and new architectures. The company has parallel design teams all over the world to keep the tick-tock strategy on track.

"Tick-tock is the engine creating today's most advanced technologies and keeps them coming out at a rapid cadence,” Otellini said. “Our customers and computer users around the world can count on Intel's innovation engine and manufacturing capability to deliver state-of-the-art performance that rapidly becomes mainstream."

Following the tick-tock strategy, a mature 32nm process will be ready for Intel’s upcoming Sandy Bridge processor. Sandy Bridge is the successor to Nehalem, though Intel hasn’t said much about the architecture, which is due in 2010.




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