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Hardware Intel Readies "Tigerton" Xeon MP
Anh Tuan Huynh (Blog) - May 18, 2007 2:53 AM
Print E-mail del.icio.us 23 comment(s) - last by zsdersw.. on May 21 at 6:49 AM
Intel prepares to launch its 65nm dual and quad-core "Tigerton" Xeon MP processors for enterprise servers

Intel is preparing to launch its upcoming 65nm Tigerton dual and quad-core Xeon MP processors. The new Intel Xeon MP E7200 and E7300-sequence processors will launch next quarter with eight different models with three different thermal envelopes no less, according to Intel’s latest roadmap.

At the top of the Tigerton ladder is the Intel Xeon MP X7350 with its 2.93 GHz clock frequency and 130 watt TDP. Right below it is the Xeon MP E7340 with a 2.4 GHz clock speed. The Xeon MP E7340 has a lower 80-watt TDP. Intel also has a low power Xeon MP L7345 clocked at 1.86 GHz with a 50-watt TDP. All three models mentioned above have 8MB of L2 cache.

Intel Quad-Core Tigerton 8MB
Model
 Core
Frequency 		L2 Cache
TDPPrice
X73502.93 GHz 8MB130W
$2301
E73402.40 GHz 8MB 80W
$1980
L73451.86 GHz8MB50W
$2301

Intel plans to launch a Xeon MP E7330 model that is similar to the E7340, but with 6MB of L2 cache as well. There are also two lower end quad-core Intel Xeon MP processors clocked at 2.13 GHz and 1.60 GHz – the E7320 and E7310. These two models have half the L2 cache as the higher end models, 4MB.

Intel Quad-Core Tigerton
Model
 Core
Frequency 		L2 Cache
TDPPrice
E73302.40 GHz 6MB80W
$1391
E73202.13 GHz 4MB 80W
$1177
E7310
1.60 GHz4MB80W
$856

Intel only has two dual-core Tigerton Xeon MP models in the pipeline. The new Intel Xeon MP E7220 and E7210 clock in at 2.93 GHz and 2.40 GHz, respectively, and share the same 80-watt TDP rating as most of the quad-core lineup. These dual-core Tigerton Xeon MP processors feature 8MB of L2 cache.

Intel Dual-Core Tigerton
Model
 Core
Frequency 		L2 Cache
TDPPrice
E72202.93 GHz 8MB80W
$1177
E7210
2.40 GHz8MB80W
$856

All upcoming Tigerton Xeon MP models feature a 1066 MHz front-side bus. Unlike the previous generation Tulsa 7100-series, Intel has killed off HyperThreading. Nevertheless, Intel Virtualization and Intel 64 technologies carry on in Tigerton.

Expect Intel to debut Tigerton Xeon MP E7300 and E7200-sequence processors next quarter on the new Caneland platform with the Intel 7300 chipset. Intel’s upcoming Caneland platform supports up to four Xeon MP processors with up to 256GB of DDR2-533 FB-DIMM memory. Companies requiring more processing power can also turn to IBM’s upcoming X4 chipset with support for up to 32 processors.

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1066 MHz front-side bus
By duploxxx on 5/18/2007 6:57:29 AM , Rating: 2
Argh there goes the nice speed advantage. Instant kill on heavy io/mem applications and bye bye on VMWare, we were waiting for this platform to see how it will perform, but it will be even worse then clovertown. Speedincrease is nice but FSB decrease is unbelievable.




RE: 1066 MHz front-side bus
By zsdersw on 5/18/2007 9:04:43 AM , Rating: 2
How in the hell do you know how it will perform?

Caneland isn't four processors, each with four cores, on a single FSB.. or even two FSBs.

See how the actual performance numbers look before you write off the platform from a performance perspective.


RE: 1066 MHz front-side bus
By Viditor on 5/19/2007 10:16:46 PM , Rating: 2
quote:
Caneland isn't four processors, each with four cores, on a single FSB.. or even two FSBs

Yes and no...
It's 4 processers (actually 8 DC processors on 4 chips) that use 4 independant connections to the chipset, but there is still only a single FSB (connection to system memory), and all interchip communication must still go through a single point...
The 64MB snoop will help, but it doesn't fix the scaling problem...


RE: 1066 MHz front-side bus
By zsdersw on 5/20/2007 8:42:48 AM , Rating: 3
You should reserve authoritative judgement until the platform is released and performance comparisons are done.


RE: 1066 MHz front-side bus
By Viditor on 5/21/2007 1:29:19 AM , Rating: 2
quote:
You should reserve authoritative judgement until the platform is released and performance comparisons are done

A fair point, but the only real question here is degree (which IS a big question, so I agree with you).
To be clear, while it's pretty much a lock that there will still be a scaling bottleneck, we will have no idea how big or small it is until release...


RE: 1066 MHz front-side bus
By mrdelldude on 5/18/2007 9:30:51 AM , Rating: 2
"Intel’s upcoming Caneland server platform features a new point-to-point connection between processors and the chipset allowing the processors to be grouped together."
http://www.dailytech.com/article.aspx?newsid=4704

"Tigerton processors will be backed by Intel’s upcoming Clarksboro chipset which moves away from the current dual-independent bus architecture. This should resolve bottlenecks currently associated with Intel’s shared front-side bus that requires two processors to share a single bus."
http://www.dailytech.com/article.aspx?newsid=4659

"In addition, servers based on Tigerton will use the Clarksboro chipset. Clarksboro eliminates the dual-independent bus structure used on current Tulsa-class servers and replaces it with a dedicated link between each quad-core chip and the chipset."
http://news.com.com/Intel+shows+off+sweet+16+serve...


RE: 1066 MHz front-side bus
By Viditor on 5/19/2007 10:03:18 PM , Rating: 2
Thanks for the links mrdelldude...
I've read through them (and everything else currently available on Clarksboro), and it appears that it's probably still going to be a big problem for Intel...

Clarksboro will:

1. connect all 4 processers to the chipset individually just as the "dual FSB" does with the DP chipset
2. have a 64MB snoop filter onboard
3. run at 1066 Mhz

With that however, Intel's scaling problems should still remain...
While the 64MB snoop filter will certainly help with memory latency, you still have

1. all cores connecting to system memory through a single memory controller
2. all interchip communication (including the connections between the 2 dual cores on each quad) must go through that single bottleneck

The scaling of cores on current Woodcrest platforms above 4 cores is absolutely terrible (by comparison), and there really isn't anything in Intel's roadmap to address this until CSI chips are released at the end of 2008...


RE: 1066 MHz front-side bus
By zsdersw on 5/20/2007 8:55:32 AM , Rating: 2
Have you given any thought to what you'll use to pooh-pooh Intel and cheerlead for AMD after CSI is released, Viditor? I'm curious about what's next for you..


RE: 1066 MHz front-side bus
By Viditor on 5/21/2007 1:38:59 AM , Rating: 2
quote:
Have you given any thought to what you'll use to pooh-pooh Intel and cheerlead for AMD after CSI is released, Viditor?


I guess it depends on what kind of pooh-pooh Intel releases...:) (sorry, I couldn't resist...)

I can see that when you can't discuss the facts anymore you resort to the old "call him a fanboy" response...
Why don't we wait and see when CSI actually comes out? Who knows, it might be delayed (again) or it might even be cancelled.


RE: 1066 MHz front-side bus
By zsdersw on 5/21/2007 6:49:39 AM , Rating: 2
No, it was an honest question. The only thing I've seen you constantly and consistently use as a reason to sing the praises of AMD and be anti-Intel is HyperTransport. Soon, when Intel has something very similar, you'll likely have to find some other reason to be as biased toward AMD as you are.. and I'm wondering what that reason will be.

As for discussing the facts, that's what I did up above in response to a post of yours that was largely identical to this one in substance and intent.


Rip Off Coming
By Metroid on 5/18/2007 5:21:22 AM , Rating: 2
The prices speak for it.




RE: Rip Off Coming
By venny on 5/18/2007 5:47:31 AM , Rating: 2
2301! wow!


RE: Rip Off Coming
By Metroid on 5/18/2007 6:15:26 AM , Rating: 2
What calls me attention is that X7350 is 2.93 GHz with a TDP of 130 watts and X7345 is lower clocked with a TDP of 50 watts and both are in the price tag of $2301. Kind strange that. I reckon something different and also the prices should be different on basis.


RE: Rip Off Coming
By dcalfine on 5/18/2007 7:08:35 AM , Rating: 3
an 8MB cache is droolworthy


RE: Rip Off Coming
By defter on 5/18/2007 6:46:55 AM , Rating: 3
???

A while ago both AMD and Intel were charging about $4000 for their fastest 4-way capable CPU. ~$2000 is relatively cheap price.


RE: Rip Off Coming
By Viditor on 5/19/2007 10:11:23 PM , Rating: 2
I agree with Defter...$2000 for an MP chip isn't really an exorbitent amount.
Keep in mind that the only market that uses these are the higher end corporate and enterprize markets. Even rendering workstations won't use 16 cores (except in very rare situations).


RE: Rip Off Coming
By Targon on 5/18/2007 8:27:54 AM , Rating: 2
Multi-processor CPUs always have a price premium on them, so that is the reason for the high prices. AMD has three different series for their server processors(which is the category that Xeon is in). So, you have the 4-way servers, the 2-way, and the single processor server chips.

Clock speeds and cache are a part of it, but AMD adds extra HyperTransport links on their processors as the thing that makes a 4-way chip different from a 2-way chip, and a 2-way from a single-processor chip. A 4-way Opteron has three extra HyperTransport links, one for each additional processor, and this boosts multi-processor performance.

I would be curious to see the performance differences between these Xeon processors in 4-way, 2-way, and 1-way, but also to see the performance if you just throw in normal Intel processors. Aside from cache, what are the current differences between the "regular" Intel processors and the Xeon at this point.


RE: Rip Off Coming
By JeffDM on 5/18/2007 12:49:19 PM , Rating: 2
Let's just say that you don't need it and it's not marketed towards cheapskate consumers because it's not a cheapskate consumer product.

This is for computers that have FOUR sockets, meaning that you can stuff sixteen cores into one computer. Prices for CPUs for four socket computers have always been that high. The higher end chips require more validation to make sure they work properly under a wider range of circumstances.


Slow, kludgy and hot
By DeepThought86 on 5/18/07, Rating: 0
RE: Slow, kludgy and hot
By zsdersw on 5/18/2007 10:31:43 AM , Rating: 2
Hotter than a dual-FSB solution? Definitely. Obscenely hot? I doubt it. Prone to bugs? Probably only if Blackford is, because Clarksboro is just Blackford extended to 4. Expensive? Certainly, but remember.. we're talking 4S servers; cost is hardly a prime consideration. It should be quite good on price/performance.


RE: Slow, kludgy and hot
By mrdelldude on 5/18/2007 11:02:45 AM , Rating: 2
"Intel’s upcoming Caneland server platform features a new point-to-point connection between processors and the chipset allowing the processors to be grouped together."
http://www.dailytech.com/article.aspx?newsid=4704

"Tigerton processors will be backed by Intel’s upcoming Clarksboro chipset which moves away from the current dual-independent bus architecture. This should resolve bottlenecks currently associated with Intel’s shared front-side bus that requires two processors to share a single bus."
http://www.dailytech.com/article.aspx?newsid=4659

"In addition, servers based on Tigerton will use the Clarksboro chipset. Clarksboro eliminates the dual-independent bus structure used on current Tulsa-class servers and replaces it with a dedicated link between each quad-core chip and the chipset."
http://news.com.com/Intel+shows+off+sweet+16+serve...


6MB?
By jhtrico1850 on 5/18/2007 10:28:19 AM , Rating: 2
Isn't that 45nm?




RE: 6MB?
By coldpower27 on 5/18/2007 11:04:59 AM , Rating: 2
No, these are Quad's at 65nm with some cache disableds total LV2 cache pool between the 2 dice is 8MB.


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