Last week at ISSCC, Intel was showing off private demonstrations of its quad core 65nm Xeon processors. The chips, dubbed Tigerton and Clovertown, are multi-core versions of Intel's upcoming Conroe and Merom architecture. Roadmaps from Intel have already revealed Merom will feature a 4MB L2 cache, 14 stage 4-issue pipeline and operate on just under 45W for two cores. There was no mention of clock speed, or even if all four cores were functional on the CPUs, but the demonstration did include a PC running on the processors. As to why there are two codenames for quad core CPUs, Intel representatives hinted to us that the layouts of the cores are different between the two CPUs. Intel also mentioned that the architecture used on these new processors scales well past 32 cores per chip. As of now, the architecture is still unnamed but Intel has announced the new brand-wide architecture will get a name at the Intel Developer Forum a few weeks from now. More details about the new chips here. AMD has separately announced that quad core Opteron processors will be available in 2007. AMD typically demonstrates new chipsets and processors during IDF offsite.