DailyTech - Intel, Micron Joint Venture Rolls Out 32Gb, 3bpc NAND

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Hardware Intel, Micron Joint Venture Rolls Out 32Gb, 3bpc NAND
Shane McGlaun (Blog) - August 12, 2009 2:10 PM

28 comment(s) - last by .. on Sep 1 at 9:47 AM

New NAND stores 3-bits per cell and will enter mass production in Q4

The technology world is all about partnerships for research and development of new products. These partnerships allow the companies to share in the cost of bringing new technology to market and share the risk if the product fails.

Intel and Micron have announced that their joint venture called IM Flash Technology has unveiled its latest NAND breakthrough. The company is offering 32Gb MLC NAND flash chips built using the new 34nm manufacturing method. The new NAND allows the storage of 3-bits per cell and will be used in flash drives and SSDs among other products.

IM Flash Technology reports that samples of the chip are available and mass production is expected to begin in Q4. The 34nm NAND products produced by IM Flash Technology are also used in storage for MP3 players, digital cameras, and other devices.

Intel's Randy Wihelm said, "The move to 3bpc is yet another proof point to the remarkable progress Intel and Micron have made in 34nm NAND development."

In other flash-related news, Hitachi will be offering SSDs built using 32nm NAND technology on drives that it has coming in 2010. The SSDs will be for enterprise users and offer SCSI and Fiber Channel interfaces.

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More Info...

By Aeonic on 8/12/2009 2:42:56 PM , Rating: 5

I can certainly go RTFM but it would have been useful to have some kind of overview at what significance having 3 bits per cell has. I'd be surprised if this is common knowledge, even among DT readers.

Here's a link with a little info for anyone else not really versed in the internals of NAND:
http://en.wikipedia.org/wiki/Flash_memory#Principl...

RE: More Info...

By Aeonic on 8/12/2009 2:45:45 PM , Rating: 4

And here:

http://en.wikipedia.org/wiki/Multi-level_cell

So it looks like 3 bits per cell allows cheaper memory and higher capacity, at the probable cost of some speed and reliability (but maybe negligible, who knows).

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RE: More Info...

By Laereom on 8/12/09, Rating: -1

RE: More Info...

By inighthawki on 8/12/2009 3:29:19 PM , Rating: 5

You speak for everyone now? I didn't know how 3 bits per cell affected flash memory and it was very kind of the above posts to provide further details. In fact i know quite a few people who would visit this website that haven't the slightest clue what that is either.

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RE: More Info...

By SAnderson on 8/13/2009 10:53:30 AM , Rating: 2

Reads and especially writes will be slower, its just the way NAND is designed. Toshiba's will suffer same performance hit but its not these chips that will be going into SSDs but the normal SLC/MLC chips.

There is a tradeoff in Logic area on the die due to needing to read more states per cell but then there is 50% more data per cell so overall the die size will be smaller. Unlike SLC/MLC (which is the same actual chip) this will be a separate chip. About 10-11Gb cells x3bpc to make the 32Gb chip. THAT is actually how the chips size is reduced.

And if DT actually got the news from the source it does not mention SSD anywhere in the article. For the most part it seems to be a direct copy from informationweek except for the SSD part. Go here for the actual official news link where it says these will be used in products like USB and flash cards where writes speed and endurance is less of a factor.

http://www.micron.com/about/news/pressrelease.aspx...

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RE: More Info...

By PandaBear on 8/13/2009 12:43:16 PM , Rating: 5

SLC (1 bit per cell) vs MLC (2 bit per cell) has a 2x capacity improvement for marginally increased cost. In 3 bit per cell (aka 3LC) there will be another 50% increase in capacity for literally no die size increase.

It is done by charging/discharging the floating gate in the cell to a precise voltage/charge (write) so that it can be detected later (read). It is easy if you just need to charge/discharge between on and off, harder if you want to do between 0, 1.25, 2.5, 5V, and very hard if you want 0, 0.625, 1.25, 1.925, etc... because there aren't much margin of error.

You have to do it much slower (to the point of more than 1 second per page of 48 sectors), the page size and block size becomes much larger, and a cell becomes worn out way earlier than before. Instead of having 1.25V safety margin, you now have only 0.625V. The latest data is that you can only program / erase a cell 500 cycles (vs 100k cycles in SLC and 5k cycles in 2 bit per cell MLC) without garbage collection.

ECC also needs to be much stronger. From the 6 bits back in SLC days to 12 bits in MLC to now 24-42 bits in 43nm 3LC, and 122 bits in 32nm 3LC already in the FAB. Some chips are the same (i.e Toshiba's 43 and 32nm last gen 3LC) and is only the operation mode that determines whether it was SLC/MLC/3LC, but to meet performance target (i.e. SDHC speed class 4), the next gen chips for 3LC will be dedicated, custom design that cannot be SLC or 2LC.

That's all I can say in the public domain (since every one that uses Toshiba memory knows them already). Anything beyond this is proprietary.

PandaBear - a SanDisk engineer

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RE: More Info...

By SAnderson on 8/13/2009 2:07:58 PM , Rating: 2

I'm sure very few people knew that your SLC/MLC/3LC chips were exactly the same, I didn't. I'm sure there are many out there that don't know that IMFT's SLC and MLC chips are the same. Maybe one could figure out both by comparing the die sizes from press releases and white papers. I've at least never read any online news about either manufactures chips being one in the same.

If Toshiba is truly using the same die for all 3 types then they are losing out on 50-100 die per wafer with extra logic for MLC/3LC.

It may be nice that you can use the same physical die for SLC/MLC/3LC but 3LC will not be a normal 2^x number of bits, 16Gb, 32Gb and 48Gb. Instead make your 2^x chips the same and your 3LC 10-11Gb (a smaller die size) and only burden that die with the extra logic (sense amps, DDC) to read the extra required voltages. As you mentioned it should have its own dedicated design to keep die size to the min.

Yes the read/write voltages are much closer with multiple bits per cell but its even harder than just dividing the range in half as not all are "spaced" equally. One may 0.3,another 0.5, 0.7 and 1v or w/e. This is where your implant doses need to be spot on to keep Vt in range and ECC is critical.

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RE: More Info...

By PandaBear on 8/13/2009 5:28:09 PM , Rating: 4

Agree with most of your points, and based on public info your assumption is correct. In reality they aren't and I can't tell you why due to them being proprietary info.

Usually the cell design between SLC/MLC have the same goal: maximum charge retention, charge/discharge speed, and life cycle. What you mentioned about 16Gb vs 32Gb vs 48Gb capacity per die differences differences, not aligned to the typical 2/4/8/16GB size end product is not that big of a deal because of 1) 3LC has lower yield so you have to get factor in extra amount for your need, and 2) not every single block on a die is good and you have to factor in the loss.

In practice, at least based on the common public practice, a flash die is tested as SLC / MLC / 3LC and sorted into capacity that guarantee a certain number of good blocks. The end result still 8Gb, 16Gb, and 32Gb die of SLC/MLC/3LC and the die is binned down to the maximum quality / price the FAB can be sold at. Ideally they will try to bin all 3LC wafer die into 3LC, and those that fail would be binned into 2LC. The 2LC wafer die has different wafer design that are targeted for 2LC rather than a one size fits all approach. You can think of it as AMD trying to sell X3 processors out of bad X4, but they also have dedicate X3 processors that can be neutered into X2 processors.

I can say that the voltages between different "levels" that represents the MLC/3LC signals are not linear, but beyond that is trade secret that I cannot share.

Hint: go search for patents and see what people do to get around these problems.

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RE: More Info...

By PandaBear on 8/13/2009 5:42:52 PM , Rating: 3

One more information I can share with you that is also in the public domain (circulating around DRAM exchange pricing):

SanDisk/Toshiba specialized in higher bit per cell counts, and they are the only one shipping 3LC memory since the 56nm generation, is shipping 3LC in 43nm generation, and already has 3LC 32nm generation but no one other than SanDisk has the controller that can use it (too slow and too high of an ECC count).

Samsung still has 80% of their nand in 50nm and the remaining in 40nm, and they ship mainly 2LC and SLC.

Micron/Intel skipped 40nm and therefore has problem jumping directly into 34nm, and only recently did they get the 34nm yield good enough. They sell a lot of 2LC and SLC, but no one that I know of knows the quality of their 3LC.

One of the main reason SanDisk bought M-System a few years ago is a key patent that it has on 3LC and 4LC memory usage. Samsung wanted to buy SanDisk because of this patent last year. Without this patent you will have a hard time developing a controller for 3LC in the 30-20nm generation that is fast enough for any useful purposes.

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RE: More Info...

By SAnderson on 8/14/2009 11:46:12 AM , Rating: 2

Sure not every block is good on every single die, but that's where redundancy comes into play. Build in a few extra WL and Bitlines on each die. The die size hit is minimal but it can save die here and there by blowing fuses. It also allows the controller to swap out cells that fail in the field for good ones. There's always that trade off. Where that line lies but it seems like a good one.

Relying on downgrading a product built for 3LC or AMD's x4 to achieve enough income to survive is an overall bad practice. Making a faster SLC/MLC chip and a dedicated smaller 3LC chip is better overall. As for common practices AFAIK Toshiba is the only one selling 3LC in the market so that kinda limits on who is practicing this common practice. :)

Yes I do know the voltages are not linear and I as well cannot comment further.

I believe if IMFT is going to sell 3LC to the market that Toshiba is not the only one with a controller for 3LC. They did develop their own controller for the flash in the Intel branded drives so its a good guess they have their own 3LC controller.

IMFT's 34nm yield is and has been fine. They did skip a few nodes as they went from 7xnm to 50nm to 34nm which put them from lagging in technology to a leader. The next node will be a 2xnm generation as publically mentioned.

3LC has its uses in other areas besides those looking for speed/endurance. USB and flash cards are mentioned in the link I posted above and seems to be one of Sandisk's main arenas.

I doubt Samsung is still shipping mostly 5xnm parts, the cost structure just isnt there anymore. Besides they have already mentioned 3xnm parts as well.

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RE: More Info...

By PandaBear on 8/14/2009 12:47:54 PM , Rating: 2

Ah.... so you work for a Nand company too, nice. Intel? Micron? Samsung?

I read an article 2 weeks ago on dramexchange about Samsung still ship 80% of their die in 50nm generation, not sure if it is still valid or if they are old news.

Regarding to down grading 3LC to MLC memory: it is still a maturing technology and therefore the yield is not perfect. While most of them are still meeting the 3LC requirement, a huge percentage of them are binned into MLC still. Of course, no sane FAB would make most of their MLC from a 3LC mask and they still have dedicate MLC/SLC mask for that. So your point is valid as well.

Another thing you have to look at also, is in a FAB yield ramp up time and R&D progress is also very important. Sometimes the FAB would spin a new set of masks to fix a problem, increase yield, or adjust the size/performance to make the end product more usable. One of the main reason you don't see too many 3LC outside Toshiba's own controller is because of the odd block size (not being 2 or 4MB, but 6MB) causing memory access across block boundary, thus very slow in the SD Speed Class qualification test. Most people have problems using 3LC in SDHC Class 4 (the minimum requirement) card because of this, and everyone in the SD standard committee is aware of it.

Based on what I understand, Phison can do 56nm 3LC and maybe 43nm 3LC, but no 3rd party controller house in the market today can do 32nm 3LC yet (maybe in their lab, but at least not selling in volume yet).

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RE: More Info...

By SAnderson on 8/17/2009 10:54:34 AM , Rating: 2

Yes I do, Micron.

I guess I need to visit dramexchange more often. :) Today on semiconductor.net there was a news item mentioning Samsung is going to convert a 200mm DRAM fab into Cu BEOL for NAND at 3xnm production as their 5xnm production at Austin was not using Cu for BEOL. It was also mentioned its the biggest US NAND fab so it may account for a large portion of their 5xnm production.

I'm not sure what type of controller work is going on at Micron/Intel to use the announced 3LC chips in USB/SD cards. Not exactly my area.

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RE: More Info...

By Souka on 8/12/2009 7:32:00 PM , Rating: 2

It's 50% more bits per cell than 2bpc...duh!

;)

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doubt 3bpc nand will be in SSDs soon

By menting on 8/12/2009 4:40:55 PM , Rating: 2

speed and MTBF of NAND flash goes way down with 3bpc compared to MLC(2bpc) and SLC. Seriously doubt Intel will put it in their SSDs anytime soon.

RE: doubt 3bpc nand will be in SSDs soon

By PandaBear on 8/13/2009 12:46:06 PM , Rating: 2

No one can do 3bpc on an SSD because it only has barely enough performance to do a bottom of the market performance and durability.

Any performance card would be at least 2bpc. SSD need at least 2bpc to SLC.

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Harharhar

By rcpratt on 8/12/2009 2:13:45 PM , Rating: 2

Only took DT four hours to fix a reading mistake, calling these "32nm NAND" drives.

3 bits per cell not very reliable

By flipsu5 on 8/12/09, Rating: 0

RE: 3 bits per cell not very reliable

By flipsu5 on 8/12/2009 4:37:13 PM , Rating: 2

quote:
There is going to be a tradeoff in bit capacity and reliability. You may have to buy 10 MLCs to backup the data on an SLC of the same chip area and half the capacity.

Actually for 3bpc it would be a third the capacity, but much less than 1/10 the number of reliable uses. The criterion for reliability is tighter because the charge levels are much easier to overlap.

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For consumers, 3bit is nice

By Hacp on 8/13/2009 7:28:50 AM , Rating: 2

If you're running a server, by all means go SLC. However, for consumers, 3bit fits the bill nicely. By the time the drive breaks, there will be cheaper, higher capacity drives ready to replace it.

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