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An document consistent with Intel roadmaps details the company's upcoming 6-core processor

The same slide deck details side-by-side projections of Nehalem with other AMD and Intel processors

George Out estimates the floating point point and integer performance by extrapolating datapoints on the slid  (Source: ZDNet)
Sun confirms what Intel has been dying to tell us, at least off the record

Late last month in Austria, Intel presented Sun with roadmaps discussing details of its upcoming server platforms, including the fairly secret Xeon Dunnington and Nehalem architectures. Unfortunately for some, this presentation ended up on Sun's public web server over the weekend.

Dunnington, Intel's 45nm six-core Xeon processor from the Penryn family, will succeed the Xeon Tigerton processor.  Whereas Tigerton is essentially two 65nm Core 2 Duo processors fused on one package, Dunnington will be Intel's first Core 2 Duo processor with three dual-core banks. 

Dunnington includes 16MB of L3 cache shared by all six processors. Each pair of cores can also access 3MB of local L2 cache.  The end result is a design very similar to the AMD Barcelona quad-core processor; however, each Barcelona core contains 512KB L2 cache, whereas Dunnington cores share L2 cache in pairs.

To sweeten the deal, all Dunnington processors will be pin-compatible with Intel Tigerton processors, and work with the existing Clarksboro chipset.  Intel's slide claims this processor will launch in the second half of 2008 -- a figure consistent with previous roadmaps from the company.

The leaked slide deck also includes more information about Intel's Penryn successor, codenamed NehalemNehalem is everything Penryn is -- 45nm, SSE4, quad-core -- and then some.  For starters, Intel will abandon the front-side bus model in favor of QuickPath Interconnect; a serial bus similar to HyperTransport.

Perhaps the most ambitious aspect of Nehalem? For the first time in 18 years Intel will pair its processors cores up with on-die memory controllers.  AMD made the switch to on-die memory controllers in 2003. For the next three years its processors were almost unmatched by Intel's offerings.  The on-die memory controller can't come a moment too soon. Intel will also roll out tri-channel DDR3 with the Nehalem, and all that extra bandwidth can only be put to use if there are no bottlenecks.

As noted by ZDNet blogger George Ou, the slides contain some rudimentry benchmarks for Nehalem and other publicly available processors.  From this slide deck, Ou estimates Nehalem's SPEC*fp_rate_base2006 at 163 and the SPEC*int_rate_base2006 at 176.  By contrast, Intel's fastest Harpertown Xeon X5482 pulls a measly 80 and 122 SPEC fp and int rate_base2006.

The Nehalem processor more than doubles the floating point performance of its current Penryn-family processors.  Ou adds, "We’ll most likely know by the end of this year what the actual scores are, but I doubt they will be more than 5% to 10% off from these estimated projections."

It's important to note that these estimates are not actual benchmarks.  Intel's document states, "Projections based on *SPECcpu2006 using dual socket Intel Xeon 5160 Processor performance as the baseline." As discussed on DailyTech before, simulated benchmarks offer little substance in favor of the real deal.

As of February 2008, the company plans to launch Nehalem in Q4 2008.

Sun has since removed the slide deck from its website.

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On-die memory controller?
By Storkme on 2/25/2008 6:31:24 AM , Rating: 2
Out of interest, what's so special about an on-die memory controller? What's the alternative, and how does it compare?

RE: On-die memory controller?
By zsdersw on 2/25/2008 6:49:19 AM , Rating: 2
The alternative is off-die memory controllers (in the Northbridge), which is what Intel has been using for a long time.

RE: On-die memory controller?
By Gul Westfale on 2/25/2008 8:20:06 AM , Rating: 3
if it's on the motherboard then the cpu has to send a request to the northbridge chip first, andthen wait for teh requested data to arrive. with the memory controller on the same die as the cpu this wait time is eliminated. AMD has been using this on all K8 cpus, and i remember them saying that it cuts latency by 40% compared to a northbridge controller.

also, since the memory traffic passes through a dedicated bus (the on-die controller), the frontside bus is kept free for other things.

RE: On-die memory controller?
By tastyratz on 2/25/08, Rating: 0
RE: On-die memory controller?
By calyth on 3/3/2008 11:39:28 PM , Rating: 2
Uh. Memory latency can wreak havoc on performance.
Suppose the difference between AMD and Intel's offerings is just the functional units. Then you'll see performance varies based on the benchmarks that they're executing. But if you crank up the latency, performance drops across the board.

Intel's very visible method of compensating at the moment is to use pretty giant L2 caches. The Penryn-derived Xeon has some pretty gigantic L2 cache sizes. The decrease in cache miss is not linear to the proportional to the cache size increase, but they can't really afford to have a miss. From what I've seen, the Core 2 is a more aggressive superscalar processor, issuing more instructions than Phenom. They really need to keep the memory latency in check to make sure that it can perform. There was this article on Tom's Hardware where they have 3 C2D at the same clock rate, but different cache sizes. Most application benchmarks, when there is variance in performance, the jump from 1MB to 2MB is more significant than 2MB to 4MB.

RE: On-die memory controller?
By masher2 on 2/25/2008 10:30:24 AM , Rating: 4
The disadvantage, though, of an on-die memory controller is that it forces you match a cpu to an specific memory technology. Current Intel CPUs can work equally well with DDR2, DDR3, FB-DIMMs...even DDR1, were someone to make a motherboard that supported it. With an on-die controller, new cpus will be specific to one certain type.

RE: On-die memory controller?
By eye smite on 2/25/2008 10:47:50 AM , Rating: 4
Yeah but the FSB has always been a bottleneck for intel and still is. This new controller on the chip will remove that and you'll see even higher numbers in benchmarks and performance as a result. The sacrifice of not being able to use 2 different rams as a result is a small sacrifice IMO. AMD has done well with hypertransport, lets see if intel does as well. I'm sure they will.

RE: On-die memory controller?
By rninneman on 2/25/2008 1:13:14 PM , Rating: 1
The FSB bottleneck is mostly AMD marketing. There is no desktop application that can saturate the FSB on current Intel platforms. The K8 owned the P4 because it was a more efficient core. Only certain specific server workloads benefit from the ODMC. No Intel product yet has an ODMC and they still own everything AMD makes including Barcelona.

RE: On-die memory controller?
By fic2 on 2/25/2008 6:29:25 PM , Rating: 3
Intel made up for the lack of an on-die memory controller by putting HUGE amounts of cache on the chip. With an on-die memory controller they can probably cut this back quite a bit and possibly save die space making the chip size/cost less and lower heat. Of course, this is assuming that the die space used for the on-die memory controller is less than the cache.

RE: On-die memory controller?
By Stratocaster on 2/25/2008 10:49:28 AM , Rating: 2
That's quite interesting^, thanks.

RE: On-die memory controller?
By lagomorpha on 2/25/2008 12:26:24 PM , Rating: 5
That isn't entirely true. One can make an on-die memory controller that has support for more than one type of memory, AMD just didn't with their current generation of CPUs. IIRC aren't later AMD CPUs supposed to have support for multiple memory types?

By phattyboombatty on 2/25/2008 1:34:56 PM , Rating: 3
I believe he was primarily talking about future memory types that are not finalized at the time the CPU is designed and manufactured.

It's not that much of a disadvantage for most people because by the time a new memory type is available, its usually time to upgrade your CPU too.

RE: On-die memory controller?
By Wirmish on 2/26/2008 9:01:09 PM , Rating: 2
The Barcelona/Phenom memory controler is already compatible with the DDR2 and the DDR3, but for now only the DDR2 is used.

Look for "DDR3" in this PDF:

By Anonymous Freak on 2/25/2008 4:22:22 PM , Rating: 2
Before AMD's Opteron and Athlon 64 line, all of Intel and AMD's processors used what we consider a 'conventional front side bus' to a Northbridge chip. This Northbridge chip contains the memory controller, and acts as 'traffic cop' for all memory accesses from any device, including the main CPU.

Because this chip is physically separate, and the CPU has to talk to it through a certain speed front side bus, it adds latency to memory access, and in some cases, the front side bus even bottlenecks memory access. (On Intel's laptop chipsets, the 800 MT/s front side bus is capable of only 6.4 GB/s, while the dual-channel 667 MT/s memory controller can supply 10.6 GB/s. This means that there are potentially times when the processor is 'starved' for bandwidth, even though the memory controller could supply it.

An onboard memory controller takes away latency, and removes any bottlenecks other than the raw memory bandwidth bottlenecks. (So, for example, dual-channel 1600 MT/s DDR-3 will be able to be fully utilized.) Early on when AMD implemented an on-die memory controller, they had a MAJOR memory bandwidth advantage over Intel, and has retained, until VERY recently, a major latency advantage. However, in Intel's x3x-series chipsets (G33, P35, X38, etc.,) Intel has improved caching so that the latency advantage has all but disappeared. And Intel's embrace of newer memory technologies faster than AMD (DDR-2, and now DDR-3,) have increased bandwidth, as well.

Now, if Intel sees the same benefits from their current memory performance that AMD did when they moved to onboard memory controllers, Intel will dominate all memory benchmarks by a VERY wide margin. I also wonder if the onboard FB controller on the Xeon series will negate most of FB's shortcomings (massive latency,) and make it truly competitive with modern non-FB memory?

By Trisagion on 2/25/08, Rating: 0
By dickeywang on 2/25/2008 5:26:47 AM , Rating: 1
AMD will survive. Intel doesn't want AMD to be completely eliminated, otherwise Intel itself will have to face a lot more anti-trust investigations.

By SunLord on 2/25/2008 6:05:55 AM , Rating: 2
Pretty much. It's easier for Intel to invest money into keeping AMD afloat via direct investment or through some shady third party fund. Kinda like MS investment in Apple.

It's a lot less trouble in the longer term to keep a token competitor alive then to deal with anti-trust problems that will pop up once the only competition goes away. Since to my knowledge there are only 2.5 x86 cpu manufacturers Intel, AMD, and VIA.

By Samus on 2/25/2008 7:59:50 AM , Rating: 2
AMD will just go back to being old-AMD. That is, the low-end market segment with crappy profit margins.

Their server-class CPU market is what they rely on for profit, and they hasn't been successful since they ditched Socket 939/940.

I still have a few Opteron 140 and 165 (socket 939) server's running strong in my client-base. They're as powerful and stable as anything Intel could come up with at the time, and far less expensive.

But honestly, if you were building a server now, would you choose an Opteron or a Core2-Quad based Xeon? Yea, I thought so.

By murphyslabrat on 2/25/2008 12:33:40 PM , Rating: 3
I would actually pick an Opteron-based server. First reason is cost, second is power, third is scaling across client-loads.

AMD still owns the market for most server applications, and you aren't losing anything in terms of future-proof-ness; as Intel will soon be switching sockets anyway.

By AlphaVirus on 2/26/2008 12:14:14 PM , Rating: 2
But honestly, if you were building a server now, would you choose an Opteron or a Core2-Quad based Xeon? Yea, I thought so.

If you thought Opteron then yeah you thought right.

As the person above me said.
I would actually pick an Opteron-based server. First reason is cost, second is power, third is scaling across client-loads.

Power I think would outweight costs for most companies as that is a longterm investment.

Intel will not win the server market for a long time as AMD has the proper offerings to hold on strong.

By Wirmish on 2/26/2008 9:04:29 PM , Rating: 2
Rapid answer: FB-DIMMs sucks.

By Trisagion on 2/25/2008 6:14:18 AM , Rating: 2
There's no need for any monopolistic / unfair competitive behavior if there isn't any competition, is there?

By SanLC504 on 2/25/2008 8:10:36 AM , Rating: 2
Monopolistic also means inhibiting the growth of new companies as competition. If Intel lost AMD, and VIA were the only direct competitor, that could be judged a monopoly since VIA holds less than 1% of the processor market.

By paydirt on 2/25/08, Rating: 0
By paydirt on 2/27/2008 8:01:50 AM , Rating: 2
fine bump me down, but you'll see in 5 years...

By 1078feba on 2/27/2008 11:44:35 AM , Rating: 2
An interesting point of view. I'd really like to see some supporting documentation/links. If true, it may be time to really increase my holdings in Nvidia.

I have always wondered what sort of systems Crytek used to manufacture Crysis. If the highest-end rigs current can't run it with the types of FPS numbers that one can get running, say, CoD4 with it's proprietary engine, how did Crytek know that Crysis would look "fantastic". Don't get me wrong, it does, but if the devs had to run it with all the setting turned down during various builds, how did they know? What did they use, a Cray?

By jordanclock on 2/25/2008 3:11:02 PM , Rating: 4
Monopolies aren't illegal. What is illegal is using a monopolistic advantage to ensure that no others can compete in that market. If Intel gains a monopoly by having the best processor, no one can bring forth a lawsuit for that. If Intel gains a monopoly by paying off retailers and OEMs to not sell competitors, then they'll be investigated for antitrust violations and subsequently penalized.

You have to remember, the government endorses monopolies. It's the point of patents, after all. What isn't endorsed is using that position to make sure you're the only one to ever have that position.

By Goty on 2/25/2008 10:02:10 AM , Rating: 1
People seem to forget the fact that, before the Athlon64 (and after the original Athlon), AMD was in this same position. It's processors couldn't compete directly in performance (except in games), it was low on cash, it wasn't releasing very many new SKUs, etc., and look what happened only a few years later.

By Arneh on 2/25/2008 10:36:42 AM , Rating: 2
That's because Intel made the bad decision of going for clockspeed rather than efficiency/performance with the P4.

Just look at the mobile market. Intel have dominated that for a long a time and had a great efficient chip for it many years ago (the original Banias Pentium M). If Intel had released a desktop version of the Pentium M back then with more cache/high clockspeed etc. instead of using the P4 for their desktop line, AMD's A64 wouldn't have been anywhere as dominant as it was against the P4.

By Arneh on 2/25/2008 10:44:52 AM , Rating: 2
Basically, what I'm trying to say is it'll take another huge mistake on Intel's part, a P4-like mistake, for AMD to have another chance at being the performance leader in the desktop space, and I don't see that happening anytime soon with Intel's current and near-future products.

Intel's first CPU with IMC?
By vignyan on 2/25/2008 7:07:24 AM , Rating: 2
I think this is a common fallacy. Intel had another unsuccessful processor back with an IMC. I am sure they had it... but dont recall the CPU number...

RE: Intel's first CPU with IMC?
By Master Kenobi on 2/25/2008 8:07:08 AM , Rating: 2
That processor never made it to market. Intel experimented with the idea over 10 years ago but at the time it was not a good option due to the requirement they set to keep the legacy Bus around. Simply moving the memory controller on die actually was a bigger hit in performance than leaving it on the northbridge. AMD themselves used an off-die memory controller until they moved to Hyper-Transport due to the limitations of the Bus architecture. With Nehalem Intel is also moving to the new Quickpath architecture which will allow them to move the controller on-die.

RE: Intel's first CPU with IMC?
By BSMonitor on 2/25/2008 9:37:38 AM , Rating: 3
The reason for not going on-die with a memory controller has nothing to do with the bus. The reason has to do with compatible memory types. Today, you can buy a brand new socket 775 x38 motherboard with DDR3 slots and drop in a Pentium 4/D, Celeron, Core 2 Conroe, etc... that is pin and BIOS compatible.

Because the memory controller is in the Northbridge, the motherboard determines what type of memory is compatible.

However, no AMD processor manufactured today is DDR3 compatible and none of them ever will be. The memory controller on the CPU has to be upgraded for each new memory tech. And AMD simply doesn't do this on a whim. Remember how long it took just to get away from Registered DDR or up to DDR2. Being compatible with new memory types requires all new steppings for each processor for this to happen.

RE: Intel's first CPU with IMC?
By phattyboombatty on 2/25/2008 1:52:00 PM , Rating: 2
You're saying that Intel didn't use an ODMC because it was concerned that its customers may have to upgrade more often? Intel may offer that reason to the public, but I doubt that's the real reason for not including the ODMC previously. My best guess is that with the netburst architecture Intel's primary motivation (back when the marketing dept. made the decisions instead of the engineers) was to increase the CPU clock speed as much as possible. Intel originally thought it could get to 10Ghz speeds with netburst. By keeping the memory controller separate from the CPU, Intel probably thought it could scale CPU speeds better.

If your reason for not going with the ODMC in the past is accurate, why is Intel planning on using it with its future architectures? Has Intel had a change of heart and now doesn't care if its customers purchase CPU's bound to certain memory types?

RE: Intel's first CPU with IMC?
By adwama on 2/27/2008 9:34:14 AM , Rating: 2
I agree with you that it might be a marketing tool to support their cause for not keeping MC on die.. But its a matter of fact that if your CPU has 4yr cycle and North bridge has 2yr cycle, you want to have the overall system performance to go up with newer tech.
That aside, i don't even think your explanation is even close to the one given earlier. Why would CPU freq not scale well if you want to put a IMC? It damn sure will be in a separate clock well which will have no correlation with the CPU frequency scaling... Though you will be wasting precious high-speed silicon for slower IMC :)
I agree with the FSB hypothesis... Being a 90% market holder (back then) and with scores of people developing programs, its a lot of pressure on Intel to change its architecture. I don't blame FSB... Sweet FSB made first Core2duo to Core2quad in less than 3 months and a year b4 AMD's Phenom(enal???)... which BTW the highest version in the market performs under Q6600 (not even penryn! :( )...

No taking Sides! :) Just my opinion...

RE: Intel's first CPU with IMC?
By Wirmish on 2/26/2008 9:09:27 PM , Rating: 2
However, no AMD processor manufactured today is DDR3 compatible ...

The Barcelona/Phenom memory controler is already compatible with the DDR2 and the DDR3, but for now only the DDR2 is used.

Look for "DDR3" in this PDF:

RE: Intel's first CPU with IMC?
By Roy2001 on 2/25/2008 4:39:00 PM , Rating: 2

RE: Intel's first CPU with IMC?
By clnee55 on 3/2/2008 7:16:59 PM , Rating: 2
The first Intel CPU with an ODMC is the 386SL made in 1990-91. It also included an AT controller on chip. Zenith made one laptop with 386SL but it didn't last long. The market at the time was not ready for ODMC. ODMC is not new. AMD is not the first one. The credit for AMD is pick the right time to use ODMC

By logaldinho on 2/25/2008 5:10:27 AM , Rating: 2
any idea if nehalem will be compatible with x48?

RE: anyone
By KristopherKubicki on 2/25/2008 5:11:42 AM , Rating: 5
It's not. It will need a whole new motherboard, chipset and socket.

RE: anyone
By murphyslabrat on 2/25/2008 12:41:00 PM , Rating: 2
Basically, like every other Intel upgrade...only, the socket actually has a new name this time around.

RE: anyone
By Rebel44 on 2/25/2008 5:15:01 AM , Rating: 2
No - Nehalem wil use new socket.

Dunnington four die?
By UWgrad on 2/25/2008 9:57:53 AM , Rating: 2
Is Dunnington a four die package, 3 dual core die and a L3 cache, or one hugh die?

RE: Dunnington four die?
By KristopherKubicki on 2/25/2008 11:40:53 AM , Rating: 2
This hasn't been revealed yet. I'm not exactly sure myself, though I can see arguments to both designs.

RE: Dunnington four die?
By UWgrad on 2/26/2008 1:26:30 PM , Rating: 2
Found an answer, one hugh die, 300mm^2.

Core 2 Duo, Core 2 Quad...
By VahnTitrio on 2/25/2008 3:10:02 PM , Rating: 1
Core 3 Sex?

I realize this may be server only but it seems like an appropriate name for this thing.

RE: Core 2 Duo, Core 2 Quad...
By dflynchimp on 2/25/2008 7:41:21 PM , Rating: 1
I appreciate the attempt at humor but I doubt Intel execs would care to promote that kind of image with their processors. I was going to suggest Core 3 Hex, but that too would have negative connotations.

Then again, assuming an abundance in internet pr0n traffic, these servers might just so be aptly named...

RE: Core 2 Duo, Core 2 Quad...
By cheetah2k on 2/25/2008 8:39:37 PM , Rating: 2
This CPU should be named "Core 2 Trio"

RE: Core 2 Duo, Core 2 Quad...
By adwama on 2/27/2008 9:36:53 AM , Rating: 2
i like the name Core 3 Sex... But i think they still will stick to the same dumb old name Xeon! what's with the obsession with an inert gas?? ;)

By pauldovi on 2/25/2008 9:20:02 AM , Rating: 2
For starters, Intel will abandon the front-side bus model in favor of QuickPath Interconnect; a serial bus similar to HyperTransport.

How does DailyTech know the similarities between HTT and CST? Seems like a pretty big assumption that just because they are both point to point that they are similar.

By cobalt42 on 2/25/2008 10:32:31 AM , Rating: 2
Simply by virtue of being a point-to-point protocol it is far more similar to HT than to the existing FSB. That's not speculation, it's based on public information, e.g. from Intel, here:

By the way, the legacy acronym you're looking for is CSI.

12 Core Skullrail?!?
By MasterTactician on 2/25/2008 9:28:41 AM , Rating: 2
All (2 of) those happy Skullrail buyers will probably be able to upgrade to two of these suckers, for a minor fee of what, like $1999 a piece?

"Can anyone tell me what MobileMe is supposed to do?... So why the f*** doesn't it do that?" -- Steve Jobs
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