Conventional CPU package

New bumpless build-up layer (BBUL) packaging

BBUL sample
Intel may finally use BBUL

Recent reports suggest that Intel is working on research for 32-core CPUs by 2010. The new processor will contain a total of 24MB of last-level LL cache split among processor nodes. The CPU is anticipated to contain eight processor nodes with four cores per node and 3MB of LL cache to each node. Intel says that BBUL packaging method (which was actually announced back in 2001) will be just as crucial to attaining these specifications as is reducing transistor size.

Before reaching 32-core processors, or even half that, a number of technologies must still be developed to address key bottlenecks in manufacturing processors. Specifically, Intel will finally be developing new processor packaging techniques over the next several years using BBUL. The new packaging technique will allow Intel to make a number of achievements including:
  • Increase core count
  • Increase processor frequency
  • Add other core types such as chipset or other dedicated controller
  • Lower voltage
  • Reduced inductance and electrical noise
  • Thinner, lighter packaging
  • Significant power savings
Intel says that today's packaging requires too many layers, and the processor core is exposed, making it prone to damage. Current processors place the die on top of a package, connected by C4 bumps, just like ball grid array (BGA) chips. The packaging layer itself consists of three separate layers: two outer copper interconnecting layers sandwiching a center plastic core layer with holes drilled by lasers and filled with copper. The pins that actually allow the processor to interface with a motherboard socket are attached to the bottom copper interconnection layer.

With BBUL, Intel removes top interconnect layer altogether. The processor core is actually embedded into the core layer with only its top surface exposed. The bottom interconnect layer is built-up, or "grown," from the processor core. One major limiting factor that BBUL eliminates is the need to use C4 bumps to connect the processor die to the packaging. As processors become more complex and contain more cores, more interconnects are required and as a result, C4 bumps are hitting their limit in terms of size and density.

With regard for the new massive-multi-core CPUs, other details suggest that Intel will be using more optimized "mini" cores. These cores will focus a great deal on parallel thread processing and be void of floating point processing units. Using BBUL technology, Intel will be able to embed high-speed dedicated math processors into the same package.

Some of this technology already exists today care of Sun Microsystems. In a previous report on Sun's T1000 and T2000 servers, Sun introduced the UltraSPARC T1, a multi-core processor supporting up to 8-cores. The UltraSPARC cores focus on processing concurrent threads, executing up to 4 threads simultaneously per core. A math processing unit is in the same physical die, but is not within any single core.

Along with such technologies like extreme-ultraviolet (EUV) lithography, smaller silicon gates, better interconnects, BBUL, High-K gate dielectric and better processor designs, multi-core processors are quickly becoming more mainstream. While 32-core processors are still a few years away, Intel will be introducing Kentsfield, its first quad-core processor early in 2007. Likewise, AMD will also be introducing quad-core Opteron "rev. G" processors in the same time frame.

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