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"Geneseo" accelerators are PCI-E cards
Intel claims revolutionary jump forward but takes a smaller evolutionary step first

This week during Intel's spring IDF conference in Beijing, the chip giant revealed several initiatives that it claims will give it a prominent position entering 2008. One of the most stand-out projects in the works is dubbed Geneseo, aimed at competing squarely with AMD's Torrenza technology.

Both AMD and Intel express interest in opening up their respective processor platforms to allow third-party hardware developers to produce "accelerators" that can be integrated into a system, providing specialized processing for specific tasks. Late last year, Intel responded to Torrenza during its fall IDF conference by claiming that it too will open up its server platform. Today, however, we find that while Geneseo is headed in a similar direction as AMD, there are significant differences between the two platforms.

One of the biggest announcements that AMD made about Torrenza is that it will allow companies to create accelerators that install directly into an Opteron socket -- AMD has already indicated it will be using this approach in its Fusion project. Utilizing this method, accelerators can take full advantage of the system bus as well as high-speed, low latency paths to system memory and other devices. Using Torrenza, companies can also develop accelerators that plug directly into a PCI-Express slot -- Intel's Geneseo platform only offers the later.

According to details that Intel released this week, accelerators will only connect via the PCI-Express bus. Intel claimed that this is the most cost effective way of developing an open platform.

"The majority of accelerators can be efficiently supported by PCIe," Intel revealed in its channel guidance. Currently, this statement may be true as some of the most processor intensive accelerators including graphics and specific math processors rely on PCIe.

AMD, on the other hand, states Torrenza will yield better performance by giving accelerators a direct communications path with the system processor.

Stripped of all the fancy names, Intel's Geneseo is more along the lines of an extension of the PCI-Express architecture and specification. Unlike AMD's Torrenza, Intel guidance states that Geneseo aims to simplify development time and costs -- Intel also made a note that its model is based on a more "well established compatibility model."

According to Intel roadmaps, the company hopes to deliver Geneseo systems by 2009.

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So what?
By tfk11 on 4/20/2007 2:11:44 AM , Rating: 5
We already have accelerators on the pci bus. Is there anything to this story other than a fancy marketing name for technology we've been using for years?




RE: So what?
By defter on 4/20/2007 2:39:39 AM , Rating: 1
Torrenza/Geneseo are just fancy marketing names for a faster bus for accelerators. Using HTX/PCI-E will just give you more bandwidth.


RE: So what?
By tfk11 on 4/20/2007 3:58:29 AM , Rating: 2
Exactly... I thought the whole point of Torrenza was to provide accelerators a lower latency/higher bandwidth connection than what we currenly have, which is PCI-E. Even the old PCI bus was designed with accelerators in mind (bus mastering). So how is PCI-E accelerator technology news? Am I missing something?


RE: So what?
By tfk11 on 4/20/2007 3:58:29 AM , Rating: 2
Exactly... I thought the whole point of Torrenza was to provide accelerators a lower latency/higher bandwidth connection than what we currenly have, which is PCI-E. Even the old PCI bus was designed with accelerators in mind (bus mastering). So how is PCI-E accelerator technology news? Am I missing something?


RE: So what?
By josmala on 4/20/2007 4:04:06 AM , Rating: 5
Torrenza is just not faster PCIe.
It bypasses pci protocol, and has cache coherent memory...
The cache coherence and low latencies means that it can be used with stuff that talks with processor all the time.
Its NOT about bandwith. Its all about making it reasonable for processor to give orders to accelerator, and read few values from the accelerator memory, and the give more orders to accelerator based on those values. Dependencies between reads and writes for accelerator makes this new interface needed. It doesn't make graphics accelerator stuff faster since its mostly write only device with moving of large blocks at a time. However, besides physics there are several other things that this thing could accelerate.


RE: So what?
By Justin Case on 4/22/2007 4:24:35 PM , Rating: 2
Exactly. This has nothing to do with Torrenza. In fact, the only difference between this and a classic northbridge / southbridge design is that you can hang PCIe devices (plus some mysterious "accelerators") on the northbridge instead of the southbridge.

Since there's apparently no standard for those "accelerators", I guess only Intel can make them, which means everyone else will have to use PCIe, which kind of defeats the point. It takes some load from the NB-SB link, but that's it.

The whole point of Torrenza is to give certain high-bandwidth devices (ex., GPU, vector coprocessor, PPU, etc.) direct access to the CPU(s)' hypertransport bus, _without_ going through a northbridge or a PCI layer. They can be in sockets or slots, that's not the point (they can even have their own, local, high-speed RAM). The point is to get rid of PCI's overhead (which can account for almost 20% of total bandwidth), while reducing latency and increasing the bandwidth itself.


Intel says "me too!" again
By johnsonx on 4/21/2007 12:53:24 AM , Rating: 5
While Intel certainly is leading in performance right now, don't they seem VERY "Me Too!" over the last few years? First AMD developed x86-64, and Intel said "Me Too!". AMD clearly led in developing dual core, and Intel said "Me Too!". AMD went with a lower clock speed, higher IPC architecture (as compared to NetBurst), and Intel said "Me Too!" (Core). AMD has had the on-die memory controller for years, and Intel has said "Me Too!". AMD is working on graphics integrated in the CPU die and/or package, and Intel has recently said "Me Too!". Now today, Intel has said "Me Too!" to Torrenza.

Yes, I do know that AMD had been 'Me Too'-ing Intel for years before. My AMD experience goes all the way back to the AM286. It's just interesting to see the role reversal.




RE: Intel says "me too!" again
By rbuszka on 4/21/2007 11:10:10 AM , Rating: 3
"Torrenza" is also a way cooler name than "Geneseo". The latter sounds like the name of that silly coffee maker from Philips.


RE: Intel says "me too!" again
By JeffDM on 4/27/2007 6:46:01 PM , Rating: 2
I hope it's just a codename and not the product technology name.

I thought Torrenza exploited the HyperTransport bus, I don't see how Geneseo is going to be competitive vs. just doing a PCIe card. Hypertransport would appear to remove a connection hop. I'm struggling to figure out what needs such bandwidth that it would max out an x16 slot, even graphics cards aren't using much beyond an equivalent of x8.


RE: Intel says "me too!" again
By Ringold on 4/21/2007 4:06:09 PM , Rating: 2
I agree, but I'll bring up the bane of technology leaders; first ones to market with new technology almost always get destroyed by those that come later.

Part of the reason I love AMD though is the fact that they, despite having much fewer resources, really have kept Intel playing a defensive game until only just recently. That's been a huge accomplishment.


RE: Intel says "me too!" again
By Grast on 4/23/2007 11:15:48 AM , Rating: 2
Ringhold,

I believe that most people assume that just because company A releases thier idea and development plan prior to company B. Then company A had the idea first.

1. On Die memory controller - Intel has stated numerous times in the Pentium 3,4 and no Core lineups that on-die controller would be implemented when it was needed. Intel is not copying AMD! It was a logical conclusion.

2. EM64 - I believe Intel did copy. However they copied because Itainum 64 bit pure processing did not take off like Intel expected. I believe this was mostly due to a lack of 64 bit OS from Microsoft.

Just my opinion.


torrenza socket slution not for gpu
By wetwareinterface on 4/20/2007 10:19:04 PM , Rating: 4
the point most seem to miss is that the torrenza solution is not for a desktop/gpu configuration and seem to compare it to that usage model. the point of torrenza isn't a physex chip or gpu sitting in a socket but an fpga or dsp sitting in a socket. imagine the benefits to an fpga manufacturer if the hard coding could be left out and the rom left out and the memory controller left out and the ...
basically torrenza allows manufacturers of these types of devices to concentrate on what makes their device different from a cpu and leave out all the similar circuits to a cpu and use the cpu for these tasks instead and just implement a hyper transport controller to let the cpu deal with all the little alu and memory control situations you'd need to duplicate in silicon on a fpga or dsp.

now a manufacturer can dedicate more chip real estate to parallel fp lanes or extra dsp parallelism by leaving out the parts that the cpu can do for them over there in that socket. this is about inter chip communication to a cpu to handle mundane non-specialized tasks that would get repeated on silicon in the specialized part to duplicate the same tasks like memory compares and fetches etc...

with torrenza an fpga manufacturer can get away with higher yields for the same current performance meaning higher profit. or same yield higher functioanlity higher price they can charge meaning higher profit. and let's face it getting a company onboard requires nothing more than the words you'll make more money with our approach.




By johnsonx on 4/21/2007 1:20:53 PM , Rating: 2
Ah, yes, I see what you mean. Just like an 2p opteron workstation with only 1 memory bank, the second opteron depends on the first for EVERYTHING: it's just a CPU core talking on the HT bus. Likewise a special purpose processing chip would have to implement only it's core functionality and an HT interface. Everything else would be handled by the primary CPU(s) and driver software.

While an HT interface is no trivial bit to design, it's probably already a standard building block AMD can just hand off to the chip designer.


LEADED GASOLINE IS THE ANSWER!
By wingless on 4/20/2007 7:48:16 PM , Rating: 1
We need to transition back to leaded gasoline and no less than 12:1 compression ratios and 300hp on EVERY car manufactured in the world...thatll fix the problems we have with weak ass cars and crappy acceleration.

Oh this is a debate about clean air? Cars are the LEAST OF OUR PROBLEMS when it comes to pollution. How about we concentrate on manufacturing processes, cutting down the planet's A/C(the rainforest), and the bottom trawling fishing practices that destroy the oxygen making ecosystems in our ocean. We need to concentrate on bigger problems that have conveniently been made the least visible by the media and corporations. Cars are just the most visible and easily relateable source of pollution but theyre a smaller fraction of a much bigger problem.




RE: LEADED GASOLINE IS THE ANSWER!
By wingless on 4/20/2007 7:54:32 PM , Rating: 2
ooops...

WRONG POST!


RE: LEADED GASOLINE IS THE ANSWER!
By Zoomer on 4/22/2007 9:11:15 AM , Rating: 2
Why not use diesel instead? They work well too.


Intel announces Vista SP 1
By crystal clear on 4/21/2007 1:17:31 PM , Rating: 2
quote:
Intel claims revolutionary jump forward but takes a smaller evolutionary step first


But also takes an extraordinary step by announcing the VISTA SP1.

Thank you INTEL for that early tip off.

Read this-

"In the corporate space, I believe most companies will act like Intel and do some pilots and testing today, but the deployment will actually happen when the service pack gets released in the fourth-quarter timeframe -- probably the October, November timeframe," Otellini said.

http://www.informationweek.com/news/showArticle.jh...




By crystal clear on 4/21/2007 1:35:25 PM , Rating: 2
Thank you "Otellini" for that insider information.


Folding@Home Accelerator
By Ringold on 4/21/2007 4:10:00 PM , Rating: 3
I'll take two. Thanks.




hypertransport bw more effective
By Roland702 on 4/20/2007 10:30:35 AM , Rating: 2
No doubt that with AMD's plans that having a accelerator on hyper transport will be faster then Intel's implementation. However that being said PCI-E receives and sends data at the same rate and would probably be effective with the PCI-E 2 specs.

All in all we will see the pros and cons and performance differences when some benchmarks start appearing.




R600-Tunisia
By crystal clear on 4/21/2007 11:03:50 PM , Rating: 2
AMD’s R600 media event on the 23rd and 24th April,Tunisia.

Launch date end of May-expect something from nvidia to match it (GeForce 8800 Ultra ,probably) around that time.




hm
By Russell on 4/20/07, Rating: -1