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Intel's Kentsfield CPU (top) will be the first quad core desktop chip, Clovertown will be the server equivalent - Courtesy
Intel talks of quad-core Xeons and shares thoughts on integrated memory controllers

A newly invigorated Intel is pulling out all of the stops to stay ahead of AMD these days. Intel's Core 2 Duo Extreme is putting out some rather encouraging numbers and should keep AMD working hard for the next few quarters. And shortly after aggressive pricing was revealed for Intel's new Core 2 family of processors, AMD responded with its own price cuts across the board to stay in the game. With its mainstream desktop products taken care of, and its new Core 2 mobile processors on the way, Intel is looking forward to updates to its server processors.

Intel's Woodcrest processors look to make up for the sins of the father, in this case the current Xeon, by increasing performance by 80% while lowering power consumption by 35%. Even more impressive is Intel's ramp of the Woodcrest -- by the end of 2006, Intel is expecting that 90% of the Xeon processors that it ships will be dual core. Two thirds of those dual-core offerings will be Woodcrest based according to Intel.

Just around the same time that Intel releases its quad-core Kentsfield desktop processors in Q1'07, quad-core Clovertown server processors will also make an appearance. According to Intel's Enterprise Architecture Director Dileep Bhandarkar, Clovertown will be two dual-core processors built into a single package versus AMD's single package of four cores. Bhandarkar also conceded that the lack of an integrated memory controller, like those on the AMD64 platform, does hurt performance. EWEEK reports:

Bhandarkar admitted that integrating the memory controller—which handles the flow of data to and from system memory—directly into the chip rather than housing it on a chip set would improve performance with some workloads. However, he said, Intel officials felt it was more important to bring a quad-core processor to the market before AMD does. The company expects to precede its rival by a quarter or two.

Still, Bhandarkar feels that its server products will offer enough of performance advantage that it won’t need to delve into integrated memory controllers for now. In the mean time, integrated memory controllers are definitely in the pipeline as is an integrated graphics controller, but no timeline was given for either.

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By Chillin1248 on 6/14/2006 8:47:48 AM , Rating: 3
Any news if Intel will perhaps adopt Hypertransport till CSI comes out to remain competitive in the multi-CPU server arena?

RE: CSI/Hypertransport?
By Master Kenobi on 6/14/2006 9:13:06 AM , Rating: 1
Doubtfull, Intel never was one to use the same thing its competitors use. They will go with an inhouse solution most likely.

RE: CSI/Hypertransport?
By Goty on 6/14/2006 9:32:13 AM , Rating: 1
Not one to use a competitor's technology? OK, let's think about this for a second here. I can name two technologies right off the top of my head that Intel has borrowed from AMD, namely and on-die memory controller (now, at least) and the 64-bit instruction set (and you can't say that the two instruction sets aren't identical, other than the two instruction that Intel added).

On a side note, didn't I hear something a couple of months ago to the effect that Intel was going to move to an on-die memory controller? I didn't think this was really news.

RE: CSI/Hypertransport?
By Thorburn on 6/14/06, Rating: 0
RE: CSI/Hypertransport?
By ArneBjarne on 6/14/2006 10:59:04 AM , Rating: 2
Well Hypertransport (^hint) would be another ;)

RE: CSI/Hypertransport?
By Thorburn on 6/14/2006 11:19:19 AM , Rating: 2
Hypertransport isn't an AMD invention.
They may be part of the commity but it is not something they created.
As with IMC it is if anything a DEC invention :)

RE: CSI/Hypertransport?
By Viditor on 6/14/2006 12:08:43 PM , Rating: 2
Hypertransport isn't an AMD invention.

It is actually...though you're right in that it's roots can be found in DECs point-to-point protocol. The distinguishing bit here is the coherent HT links (which are pure AMD).
Also, remember that Intel uses as many AMD patents as AMD uses of Intel's (have a look at the data from the USPTO, it's quite surprising). A lot of Conroe is based on AMD patents...

RE: CSI/Hypertransport?
By Clauzii on 6/14/2006 8:50:56 PM , Rating: 2
So did Apple only lisence HT???

RE: CSI/Hypertransport?
By czarchazm on 6/14/2006 9:58:01 AM , Rating: 2
I can name two technologies right off the top of my head that Intel has borrowed from AMD, namely and on-die memory controller

Dude, that's like saying Kodak's CMOS is using Nikon's technology because it is an imager type. On-die memory controller is just another implementation of the controller.

RE: CSI/Hypertransport?
By Viditor on 6/14/2006 12:13:58 PM , Rating: 2
On-die memory controller is just another implementation of the controller

It's not, actually...AMD's on-die MC is more like a Northbridge.

RE: CSI/Hypertransport?
By Trisped on 6/14/2006 2:30:29 PM , Rating: 2
No, it is a memory controller. It provides an interface between the CPU and the main system memory. Through an unrelated interface (HT) the CPU access the North Bridge which controls the rest of the hard ware. The North Bridge directly controls the PCIe, interfaces with the SB, and does a few other things, depending on the design.

[b]All motherboards have a north bridge[/b] to connect the CPU to the rest of the system.

RE: CSI/Hypertransport?
By Viditor on 6/15/2006 10:57:17 PM , Rating: 2
The only common function of an NB has been as an interface from the CPU to the Main Memory. This is why the speed of the bus to the NB is called the FSB. The South Bridge has always been the center for all of the other communications (with the exception of AGP).
The PCIe devices (for Intel) hang off both the NB and the SB.
For AMD systems, the NB is on the die and there is a single chip solution in the form of the MCP, though there are still some chipsets (Via) that prefer to split things up so that they can use their propietary VLink connections rather than HT.

RE: CSI/Hypertransport?
By jjunos on 6/14/2006 10:46:01 AM , Rating: 2
For those with short memories, Intel tried the entire on-die memory controller with Timna. It's not like Intel didn't think of this years ago. And not like Intel created the entire idea of the on-die memory controller.

Of course...

They cancelled Timna. Doh!

RE: CSI/Hypertransport?
By pm on 6/14/2006 11:21:43 PM , Rating: 2
OK, let's think about this for a second here. I can name two technologies right off the top of my head that Intel has borrowed from AMD, namely and on-die memory controller (now, at least)

The Intel i386SL had an integrated on-die memory controller. It was released in the early 1990's.

From a Google cache link:
The Intel 386SL microprocessor integrates a fully static processor, memory controller, ISA bus controller, EMS 4.0 hardware and system control circuitry for battery-powered systems. It offers three times the integration of Intel 386SX CPUs.

I like the sound of this
By TheLiberalTruth on 6/14/2006 8:41:50 AM , Rating: 3
Looks like Intel's finally realized that a low latency memory controller is not only desirable, but perhaps inevitable. I wonder if they'll add the on-die controller when they move to 45nm. Smaller process means space for more transistors.

RE: I like the sound of this
By The Cheeba on 6/14/2006 8:46:25 AM , Rating: 3
And Intel wouldn't need to waste all that space on cache either -- meaning more processors per wafer -- meaning cheaper CPUs. Man K8L versus Penryn/Nehalem is going to NUTS.

RE: I like the sound of this
By Trisped on 6/14/2006 1:23:56 PM , Rating: 3
First, the article is about server chips, not desktop or laptop. He also says "some" which means select jobs will benefit (like ones where the memory you want is not known until the computation is completed). Plus, with 4 cores the amount of cash needed goes up drastically. Intel's last reason for not having integrated controllers was because the space would be better used by cache. As cache requirements rise with each core and memory controllers will probably stay pretty much the same, it won't be long before Intel integrates the memory controller, though don't expect it to hit the desktop/laptop screen for a while. I also wouldn't be surprised to see L3 cache become the Intel norm before the switch over is complete.

New Socket?
By Mclendo06 on 6/14/2006 9:38:14 AM , Rating: 2
Would an on-die memory controller necessitate intel making new sockets to connect the processor to the memory? Basically, I imagine that 775 (or 771 in the case of xeons) won't be enough pins to interface with memory (reason why AMD has 940).

RE: New Socket?
By Thorburn on 6/14/2006 9:54:42 AM , Rating: 2
A new socket would certainly be necessary as none of LGA775 and I presume LGA771's pins go to the memory, only to the MCH.

RE: New Socket?
By maevinj on 6/14/2006 11:25:53 AM , Rating: 1
of course its going to need a new socket. how are they suppose to make money if they dont change sockets every couple of months.

RE: New Socket?
By Thorburn on 6/14/2006 11:50:21 AM , Rating: 2
Well if you look at the server space, where a IMC design would most likely be implemented, the previous Xeon socket lasted a good few years, infact I could take a month old Xeon board and plug a Willamette based Xeon into it.
Willamette being the 180nm chip which comfortably predates even the first announcement of the Athlon 64, let alone Opteron.....

RE: New Socket?
By Trisped on 6/14/2006 1:52:41 PM , Rating: 2
Yes, but the memory is still accessed through those pins.

I wonder....
By wingless on 6/14/2006 11:30:21 AM , Rating: 2
I like integrated mem controllers but I miss the days when all I had to do was buy a new mobo to support newer memory. I wonder what technical issues would block them from designing a mem controller that could detect and work with multiple mem types like DDR1 to DDR3....probably something very obvious but I dont know enough about mem controller tech.

RE: I wonder....
By Viditor on 6/14/2006 12:16:43 PM , Rating: 2
I like integrated mem controllers but I miss the days when all I had to do was buy a new mobo to support newer memory

What most people forget is that the ODMC is actually programmable...IIRC, AMD's plans are to allow for either DDR2 or DDR3 when using FBDimms on their next-gen chips.

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