Researchers at Infineon have tested its first 65nm multi-gate finFET architecture. The name finFET comes from the fin-looking source/drain regions on the field-effect transistor. The 65nm circuitry tested by researchers contains more than 3,000 active transistors fabricated in three-dimensional multi-gate technology.

With an approximately 30-percent smaller footprint compared to current single-gate technology with the same functions and performance, the new transistors had quiescent current, also known as leakage current, which measured a factor of 10 less. According to the researchers' calculations, this will increase the energy efficiency and battery life of portable devices up to two times compared to the 65nm technology going into production today – and this factor is expected to increase with future, smaller manufacturing processes.

“With the world's first integrated circuit in 65nm multi-gate technology, we have proven that progress can be made in the semiconductor industry not only by simply continuing to scale down,” said Prof. Dr. Hermann Eul, member of the Infineon Management Board and head of the Communication Solutions business group. “Today we are challenged to use the processes and materials available to us in a more innovative way to advance our technology as cost-efficiently as possible. Our researchers' results have been impressive indeed. And beyond that, based on the results so far, we expect that multi-gate technology could offer an excellent opportunity to continue CMOS device scaling into 32nm and below.”

To keep up with Moore’s Law, the semiconductor industry increased performance by regularly miniaturizing transistors up to the limits of what is technologically feasible. However, smaller integrated circuits have higher rates of undesirable quiescent current, leading to unnecessary energy consumption and heat production.

Even when there is no activity present and the transistor is nominally off, electrons still leak through the depletion potential barrier, which is only a few nanometers thick and only controlled from the surface by the single gate of a two-dimensional transistor. Infineon chose the route of three-dimensional packaging, so the gate electrode of the transistor now encloses the depletion potential barrier on several sides, thus offering 3 times the contact surface to ensure that the transistor can be really switched off.

Infineon isn’t the only one venturing into the third dimension. Intel previously hinted it will start using tri-gate transistors on its 32 or 22nm products.