IBM is detailing a new breakthrough in three-dimensional chip-stacking technique that allows different chip components to be packaged much closer together for faster, smaller, and lower-power systems. The company claims that the technology will extend Moore’s Law beyond its expected limits.

3D chip stacking takes chips and memory devices that traditionally sit side by side on a silicon wafer and stacks them together on top of one another. The result is a compact sandwich of components that dramatically reduces the size of the overall chip package and boosts the speed at which data flows among the functions on the chip.

The technique of 3D chips is not new, as memory manufacturers such as Samsung and NEC/Elpida/Oki are developing memory in 3D packaging. IBM’s breakthrough is that it does away with the need for long-metal wires that connect today’s chips together, instead relying on “through-silicon vias,” which are essentially vertical connections etched through the silicon wafer and filled with metal. These vias allow multiple chips to be stacked together, allowing greater amounts of information to be passed between the chips.

The technique shortens the distance information on a chip needs to travel by 1000 times, and allows for the addition of up to 100 times more channels, or pathways, for that information to flow compared to traditional chips. 

“This breakthrough is a result of more than a decade of pioneering research at IBM,” said Lisa Su, vice president, Semiconductor Research and Development Center, IBM. “This allows us to move 3-D chips from the 'lab to the fab' across a range of applications.”

The first application of this through-silicon via technology will be in wireless communications chips that will go into power amplifiers for wireless LAN and cellular applications. 3D technology will also be applied to a wide range of chips, including those running now in IBM’s servers and supercomputers. 

IBM says that it is already running chips using the through-silicon via technology in its manufacturing line and will begin making sample chips using this method available to customers in the second half of 2007, with production in 2008.

Over the past few months, IBM has had a number of major chip technology announcements and demonstrations that the company claims will extend Moore’s Law. In December, IBM announced the first 45nm chips using immersion lithography and ultra-low-K interconnect dielectrics. In January, IBM announced high-k metal gate, which substitutes a new material into a critical portion of the transistor that controls its primary on/off switching function. In February, IBM revealed its on-chip memory technology that features the fastest access times ever recorded in eDRAM. Then in March, IBM unveiled a prototype optical transceiver chipset capable of reaching speeds at least eight-times faster than optical components available today.